From 2f68e39a51031d525fb17e0e2a012ce19562c1e0 Mon Sep 17 00:00:00 2001 From: seteiro Date: Sun, 18 Oct 2026 00:52:09 +0800 Subject: [PATCH 1/3] [bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 - Adapt ESP32-C3/C6 BSP to ESP-IDF v6.1; bump RISC-V toolchain to gcc 15.2 - C6: re-enable SPI with board-local drv_spi.c; add devices.spi to CI attachconfig; drop shared drv_spi.c spi_command_t hack - C6: fix ADC oneshot multi-channel unit handle and mutex - C3: fix portTRY_ENTER_CRITICAL_SAFE expansion in portmacro.h - Compat with RT-Thread-packages/esp-idf rtt-dev used by CI: map SYSTIMER_* to SYSTIMER_LL_* (C3 and C6 board.c), accept uart_periph.h from hal/ or soc/ - Fix clang-format and cppcheck issues in the compat code Signed-off-by: seteiro Co-Authored-By: Grok --- .github/workflows/bsp_buildings.yml | 4 +- .github/workflows/manual_bsp_build.yml | 4 +- .../manual_trigger_scons_except_STM32_all.yml | 4 +- .../workflows/manual_trigger_update_all.yml | 4 +- .github/workflows/membrowse-onboard.yml | 4 +- .github/workflows/membrowse-report.yml | 4 +- bsp/ESP/.clang-format-ignore | 8 + bsp/ESP/ESP32_C3/README.md | 6 +- bsp/ESP/ESP32_C3/README_ZH.md | 6 +- bsp/ESP/ESP32_C3/docker/Dockerfile | 4 +- .../idf_port/include/freertos/portmacro.h | 61 +- bsp/ESP/ESP32_C3/idf_port/ld/sections.ld | 20 + bsp/ESP/ESP32_C3/idf_port/src/port.c | 1 - bsp/ESP/ESP32_C3/main/main.c | 6 +- bsp/ESP/ESP32_C3/rtconfig.py | 14 +- .../.ci/attachconfig/ci.attachconfig.yml | 6 + bsp/ESP/ESP32_C6/README.md | 4 +- bsp/ESP/ESP32_C6/SConstruct | 4 +- bsp/ESP/ESP32_C6/docker/Dockerfile | 6 +- bsp/ESP/ESP32_C6/idf_port/SConscript | 118 --- .../idf_port/include/freertos/portmacro.h | 194 ++-- bsp/ESP/ESP32_C6/idf_port/ld/sections.ld | 11 + bsp/ESP/ESP32_C6/idf_port/src/port.c | 1 - bsp/ESP/ESP32_C6/libraries/drivers/Kconfig | 220 ++++ bsp/ESP/ESP32_C6/libraries/drivers/SConscript | 39 + bsp/ESP/ESP32_C6/libraries/drivers/board.c | 127 +++ bsp/ESP/ESP32_C6/libraries/drivers/board.h | 27 + bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.c | 297 ++++++ bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.h | 28 + bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.c | 95 ++ bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.h | 21 + .../ESP32_C6/libraries/drivers/drv_hw_i2c.c | 135 +++ .../ESP32_C6/libraries/drivers/drv_hw_i2c.h | 32 + bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.c | 176 ++++ bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.h | 18 + bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.c | 352 +++++++ bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.h | 36 + .../ESP32_C6/libraries/drivers/drv_timer.c | 162 +++ .../ESP32_C6/libraries/drivers/drv_timer.h | 20 + bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.c | 140 +++ bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.h | 21 + bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.c | 382 +++++++ bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.h | 18 + .../ESP32_C6/libraries/drivers/sdkconfig.h | 841 ++++++++++++++++ .../ESP32_C6/libraries/drivers/sdkconfig_c6.h | 940 ++++++++++++++++++ bsp/ESP/ESP32_C6/rtconfig.py | 13 +- bsp/ESP/libraries/drivers/board.c | 25 +- bsp/ESP/libraries/drivers/drv_adc.c | 31 +- bsp/ESP/libraries/drivers/drv_spi.c | 127 +-- bsp/ESP/libraries/drivers/drv_uart.c | 10 + bsp/ESP/libraries/drivers/sdkconfig.h | 37 + bsp/ESP/libraries/drivers/sdkconfig_c6.h | 17 + tools/ci/bsp_detail.py | 2 +- tools/ci/toolchain.sh | 2 +- tools/ci/toolchain_bsp.yml | 2 +- 55 files changed, 4554 insertions(+), 333 deletions(-) create mode 100644 bsp/ESP/.clang-format-ignore create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/Kconfig create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/SConscript create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/board.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/board.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.c create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig.h create mode 100644 bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig_c6.h diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 0792d9fdf31d..3ef39ab012f0 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -287,8 +287,8 @@ jobs: - name: Install riscv32-esp-elf ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv32-esp32' && success() }} run: | - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt /opt/riscv32-esp-elf/bin/riscv32-esp-elf-gcc --version pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV diff --git a/.github/workflows/manual_bsp_build.yml b/.github/workflows/manual_bsp_build.yml index 421eb976c1ab..8ae4592c8519 100644 --- a/.github/workflows/manual_bsp_build.yml +++ b/.github/workflows/manual_bsp_build.yml @@ -128,8 +128,8 @@ jobs: - name: Install riscv32-esp-elf ToolChains if: ${{ github.event.inputs.bsp_tool_chain == 'sourcery-riscv32-esp32' && success() }} run: | - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt /opt/riscv32-esp-elf/bin/riscv32-esp-elf-gcc --version pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 85ab16cb4999..d7238d42b565 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -360,8 +360,8 @@ jobs: - name: Install riscv32-esp-elf ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv32-esp32' && success() }} run: | - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt /opt/riscv32-esp-elf/bin/riscv32-esp-elf-gcc --version pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV diff --git a/.github/workflows/manual_trigger_update_all.yml b/.github/workflows/manual_trigger_update_all.yml index 16d0d03fa15c..6f830f7eeba0 100644 --- a/.github/workflows/manual_trigger_update_all.yml +++ b/.github/workflows/manual_trigger_update_all.yml @@ -117,8 +117,8 @@ jobs: - name: Install riscv32-esp-elf ToolChains if: ${{ github.event.inputs.bsp_tool_chain == 'sourcery-riscv32-esp32' && success() }} run: | - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt /opt/riscv32-esp-elf/bin/riscv32-esp-elf-gcc --version pip3 install esptool echo "RTT_EXEC_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV diff --git a/.github/workflows/membrowse-onboard.yml b/.github/workflows/membrowse-onboard.yml index 8b30a793d892..cca0499b7070 100644 --- a/.github/workflows/membrowse-onboard.yml +++ b/.github/workflows/membrowse-onboard.yml @@ -89,8 +89,8 @@ jobs: echo "TOOLCHAIN_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin" >> $GITHUB_ENV ;; riscv32-esp-elf) - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt pip3 install --user esptool echo "TOOLCHAIN_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV ;; diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml index 74e53daac202..8a936d6aa0a9 100644 --- a/.github/workflows/membrowse-report.yml +++ b/.github/workflows/membrowse-report.yml @@ -133,8 +133,8 @@ jobs: echo "TOOLCHAIN_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin" >> $GITHUB_ENV ;; riscv32-esp-elf) - wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - sudo tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt + wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + sudo tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt echo "TOOLCHAIN_PATH=/opt/riscv32-esp-elf/bin" >> $GITHUB_ENV ;; riscv64-linux-musl-k230) diff --git a/bsp/ESP/.clang-format-ignore b/bsp/ESP/.clang-format-ignore new file mode 100644 index 000000000000..011d0a2ef9eb --- /dev/null +++ b/bsp/ESP/.clang-format-ignore @@ -0,0 +1,8 @@ +# clang-format ignore file +/ESP32_C3/idf_port/include/freertos/portmacro.h +/ESP32_C3/idf_port/src/port.c +/ESP32_C6/idf_port/include/freertos/portmacro.h +/ESP32_C6/libraries/drivers/sdkconfig.h +/ESP32_C6/libraries/drivers/sdkconfig_c6.h +/libraries/drivers/sdkconfig.h +/libraries/drivers/sdkconfig_c6.h diff --git a/bsp/ESP/ESP32_C3/README.md b/bsp/ESP/ESP32_C3/README.md index 5f61eff7d455..3051b3cead1f 100644 --- a/bsp/ESP/ESP32_C3/README.md +++ b/bsp/ESP/ESP32_C3/README.md @@ -71,7 +71,7 @@ int main(void) { ```sh wcx@tim  ~/rt-thread/bsp/ESP32_C3   esp32 ±  sudo riscv32-esp-elf-gdb # Enter gdb debugging -GNU gdb (crosstool-NG esp-2022r1-RC1) 9.2.90.20200913-git +GNU gdb (esp-gdb) 17.1_20260402 Copyright (C) 2020 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. @@ -138,8 +138,8 @@ If you want to lightly experiment with the ESP32-C3, it is recommended to quickl 1. Download the RISC-V toolchain: ```sh - wget https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz + wget https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz ``` 2. Configure the path of the toolchain: diff --git a/bsp/ESP/ESP32_C3/README_ZH.md b/bsp/ESP/ESP32_C3/README_ZH.md index c0014ac86fc5..fbd17e04f0b9 100644 --- a/bsp/ESP/ESP32_C3/README_ZH.md +++ b/bsp/ESP/ESP32_C3/README_ZH.md @@ -78,7 +78,7 @@ int main(void) { ```sh wcx@tim  ~/rt-thread/bsp/ESP32_C3   esp32 ±  sudo riscv32-esp-elf-gdb # 进入gdb调试 -GNU gdb (crosstool-NG esp-2022r1-RC1) 9.2.90.20200913-git +GNU gdb (esp-gdb) 17.1_20260402 Copyright (C) 2020 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. @@ -147,8 +147,8 @@ Type "apropos word" to search for commands related to "word". 1. 下载 RISC-V 工具链： ```sh - wget https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz - tar xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz + wget https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz + tar xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz ``` 2. 配置工具链的路径： diff --git a/bsp/ESP/ESP32_C3/docker/Dockerfile b/bsp/ESP/ESP32_C3/docker/Dockerfile index 1382c5cd3856..219ece9e1cc6 100644 --- a/bsp/ESP/ESP32_C3/docker/Dockerfile +++ b/bsp/ESP/ESP32_C3/docker/Dockerfile @@ -22,8 +22,8 @@ USER dev WORKDIR /home/dev # 3. Install esp-idf toolchains -RUN wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz && \ - sudo tar -xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt +RUN wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz && \ + sudo tar -xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt # 4. Clone RT-Thread and switch master RUN git clone https://github.com/RT-Thread/rt-thread.git && \ diff --git a/bsp/ESP/ESP32_C3/idf_port/include/freertos/portmacro.h b/bsp/ESP/ESP32_C3/idf_port/include/freertos/portmacro.h index 875d4e99711e..f1c7461e565e 100644 --- a/bsp/ESP/ESP32_C3/idf_port/include/freertos/portmacro.h +++ b/bsp/ESP/ESP32_C3/idf_port/include/freertos/portmacro.h @@ -86,6 +86,39 @@ typedef rt_ubase_t UBaseType_t; typedef rt_tick_t TickType_t; #define portMAX_DELAY (TickType_t) RT_TICK_MAX +/* + * FreeRTOS V11 definitions that ESP-IDF v6.1 headers expect but the + * FreeRTOS-Wrapper kernel (FreeRTOS V10.4.6) does not provide. + */ +/* RISC-V has no privilege levels, so the annotation expands to nothing. */ +#ifndef PRIVILEGED_FUNCTION +#define PRIVILEGED_FUNCTION +#endif +/* FreeRTOS V11 renamed nothing here: `StaticList_t` is just an alias of + `struct xLIST`. Used by components/esp_ringbuf/include/freertos/ringbuf.h. */ +#ifndef RT_FREERTOS_WRAPPER_STATIC_LIST_T +#define RT_FREERTOS_WRAPPER_STATIC_LIST_T +#include "freertos/list.h" +typedef List_t StaticList_t; +#endif + +/* + * ESP-IDF v6.1's components/esp_ringbuf blocks on the FreeRTOS task event + * lists, which FreeRTOS V11 provides and FreeRTOS-Wrapper does not. + * components/rtthread/scons/event_list.c implements the two functions below on + * top of the wrapper's list implementation; the declarations have to be visible + * here because esp_ringbuf calls them after a plain . + * vTaskInternalSetTimeOutState() already exists in the wrapper's tasks.c but is + * not declared in its task.h. + */ +void vTaskPlaceOnEventList(List_t *const pxEventList, TickType_t xTicksToWait); +BaseType_t xTaskRemoveFromEventList(List_t *const pxEventList); +/* The wrapper's tasks.c defines this with TimeOut_t, which is a typedef of + `struct xTIME_OUT` in its freertos/task.h. Spell the tag out, because + task.h is not included here and a different tag would be a different type. */ +struct xTIME_OUT; +void vTaskInternalSetTimeOutState(struct xTIME_OUT *const pxTimeOut); + struct rt_semaphore_wrapper { struct rt_semaphore sem; @@ -245,6 +278,32 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) return (BaseType_t) esp_cpu_get_core_id(); } +/* + * The ESP-IDF v6.1 refers to StaticStreamBuffer_t, + * which FreeRTOS V11 defines in its FreeRTOS.h. The FreeRTOS-Wrapper kernel + * is V10.4.6 and provides no stream buffers, so nothing in the RT-Thread + * scons build can allocate one; the type only has to exist for the headers + * to parse. Same layout as ESP-IDF's components/freertos/FreeRTOS-Kernel. + */ +#ifndef RT_FREERTOS_WRAPPER_STATIC_STREAM_BUFFER_T +#define RT_FREERTOS_WRAPPER_STATIC_STREAM_BUFFER_T +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[4]; + void * pvDummy2[3]; + uint8_t ucDummy3; +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; +#endif +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + void * pvDummy5[2]; +#endif + portMUX_TYPE xDummyStreamBufferLock; +} StaticStreamBuffer_t; +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; +#endif + /* ------------------------------------------- FreeRTOS Porting Interface ---------------------------------------------- @@ -290,7 +349,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) portEXIT_CRITICAL(mux); \ } \ }) -#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portENTER_CRITICAL_SAFE(mux, timeout) +#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) // ---------------------- Yielding ------------------------- diff --git a/bsp/ESP/ESP32_C3/idf_port/ld/sections.ld b/bsp/ESP/ESP32_C3/idf_port/ld/sections.ld index b49bba2ca234..7c711187b740 100644 --- a/bsp/ESP/ESP32_C3/idf_port/ld/sections.ld +++ b/bsp/ESP/ESP32_C3/idf_port/ld/sections.ld @@ -17,6 +17,14 @@ SECTIONS * RTC fast memory holds RTC wake stub code, * including from any source file named rtc_wake_stub*.c */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + KEEP(*(.rtc_reserved*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_iram_seg + .rtc.text : { . = ALIGN(4); @@ -134,6 +142,8 @@ SECTIONS _iram_start = ABSOLUTE(.); /* Vectors go to start of IRAM */ ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); + _vector_table_start = ABSOLUTE(.); + KEEP(*(.exception_vectors_table.text)); KEEP(*(.exception_vectors.text)); . = ALIGN(4); @@ -201,6 +211,8 @@ SECTIONS *libpp.a:(.wifiorslpiram .wifiorslpiram.*) *libpp.a:(.wifirxiram .wifirxiram.*) *libpp.a:(.wifislprxiram .wifislprxiram.*) + *libpp.a:(.wifiextrairam .wifiextrairam.*) + *libnet80211.a:(.wifiextrairam .wifiextrairam.*) *riscv?interrupt.*(.literal .literal.* .text .text.*) *riscv?vectors.*(.literal .literal.* .text .text.*) *librtc.a:(.literal .literal.* .text .text.*) @@ -519,8 +531,16 @@ SECTIONS soc_reserved_memory_region_end = ABSOLUTE(.); /* System init functions registered via ESP_SYSTEM_INIT_FN */ _esp_system_init_fn_array_start = ABSOLUTE(.); + _esp_sys_init_fn_start = ABSOLUTE(.); KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_sys_init_fn.*))) _esp_system_init_fn_array_end = ABSOLUTE(.); + _esp_sys_init_fn_end = ABSOLUTE(.); + + . = ALIGN(4); + _esp_libc_clock_array_start = ABSOLUTE(.); + KEEP (*(.esp_libc_clock_desc)) + _esp_libc_clock_array_end = ABSOLUTE(.); /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; diff --git a/bsp/ESP/ESP32_C3/idf_port/src/port.c b/bsp/ESP/ESP32_C3/idf_port/src/port.c index fb5321fe1463..c296c999a04a 100644 --- a/bsp/ESP/ESP32_C3/idf_port/src/port.c +++ b/bsp/ESP/ESP32_C3/idf_port/src/port.c @@ -44,7 +44,6 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_attr.h" diff --git a/bsp/ESP/ESP32_C3/main/main.c b/bsp/ESP/ESP32_C3/main/main.c index 68ddae8641b4..393db9865b9a 100644 --- a/bsp/ESP/ESP32_C3/main/main.c +++ b/bsp/ESP/ESP32_C3/main/main.c @@ -13,13 +13,15 @@ #include #include #include +/* esp_timer_init() is called under BSP_USING_BLE; ESP-IDF v6.1's header + * chain no longer declares it implicitly. */ +#include "esp_timer.h" #ifdef BSP_USING_BLE void app_main() { - while(1) + while (1) { - } } #endif /* BSP_USING_BLE */ diff --git a/bsp/ESP/ESP32_C3/rtconfig.py b/bsp/ESP/ESP32_C3/rtconfig.py index 537d12fee99b..a87a2ec87f70 100644 --- a/bsp/ESP/ESP32_C3/rtconfig.py +++ b/bsp/ESP/ESP32_C3/rtconfig.py @@ -16,7 +16,7 @@ if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'~/.espressif/tools/riscv32-esp-elf/esp-2022r1-11.2.0/riscv32-esp-elf/bin' + EXEC_PATH = r'~/.espressif/tools/riscv32-esp-elf/esp-15.2.0_20251204/riscv32-esp-elf/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -41,8 +41,16 @@ OBJCPY = PREFIX + 'objcopy' STRIP = PREFIX + 'strip' - DEVICE = ' -nostartfiles -march=rv32imc --specs=nosys.specs -fasynchronous-unwind-tables ' - CFLAGS = DEVICE + '-include ../../components/libc/compilers/common/include/sys/ioctl.h -gdwarf-4 -ggdb -Og ' + # ESP-IDF v6.1 / binutils >= 2.41 no longer imply the Zicsr/Zifencei + # extensions in `-march=rv32imc`, so spell them out. + DEVICE = ' -nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs -fasynchronous-unwind-tables ' + # RT-Thread's rt_uint32_t/rt_tick_t are layout compatible with the + # toolchain's uint32_t but not the same type (`unsigned int` vs + # `long unsigned int` on riscv32 with GCC 15). ESP-IDF v6.1 sources + # mix both, and GCC >= 14 promotes incompatible-pointer-types and + # int-conversion from warnings to errors. + CFLAGS = DEVICE + '-Wno-error=incompatible-pointer-types -Wno-error=int-conversion ' + CFLAGS += '-include ../../components/libc/compilers/common/include/sys/ioctl.h -gdwarf-4 -ggdb -Og ' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' idf_path = find_package_path(BSP_ROOT, 'ESP-IDF-latest', relative_to=BSP_ROOT, pathsep='/') LFLAGS = DEVICE + ' -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32C3=0 -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T idf_port/ld/memory.ld -T idf_port/ld/sections.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.libgcc.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.newlib.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.version.ld -T ' + idf_path + '/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3.ld -T ' + idf_path + '/components/soc/esp32c3/ld/esp32c3.peripherals.ld -Wl,--wrap=_Unwind_SetEnableExceptionFdeSorting -Wl,--wrap=__register_frame_info_bases -Wl,--wrap=__register_frame_info -Wl,--wrap=__register_frame -Wl,--wrap=__register_frame_info_table_bases -Wl,--wrap=__register_frame_info_table -Wl,--wrap=__register_frame_table -Wl,--wrap=__deregister_frame_info_bases -Wl,--wrap=__deregister_frame_info -Wl,--wrap=_Unwind_Find_FDE -Wl,--wrap=_Unwind_GetGR -Wl,--wrap=_Unwind_GetCFA -Wl,--wrap=_Unwind_GetIP -Wl,--wrap=_Unwind_GetIPInfo -Wl,--wrap=_Unwind_GetRegionStart -Wl,--wrap=_Unwind_GetDataRelBase -Wl,--wrap=_Unwind_GetTextRelBase -Wl,--wrap=_Unwind_SetIP -Wl,--wrap=_Unwind_SetGR -Wl,--wrap=_Unwind_GetLanguageSpecificData -Wl,--wrap=_Unwind_FindEnclosingFunction -Wl,--wrap=_Unwind_Resume -Wl,--wrap=_Unwind_RaiseException -Wl,--wrap=_Unwind_DeleteException -Wl,--wrap=_Unwind_ForcedUnwind -Wl,--wrap=_Unwind_Resume_or_Rethrow -Wl,--wrap=_Unwind_Backtrace -Wl,--wrap=__cxa_call_unexpected -Wl,--eh-frame-hdr -Wl,--wrap=__gxx_personality_v0 -Wl,--cref -Wl,--defsym=IDF_TARGET_ESP32C3=0' diff --git a/bsp/ESP/ESP32_C6/.ci/attachconfig/ci.attachconfig.yml b/bsp/ESP/ESP32_C6/.ci/attachconfig/ci.attachconfig.yml index f2e9ee97d34e..ddb97aec82db 100644 --- a/bsp/ESP/ESP32_C6/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/ESP/ESP32_C6/.ci/attachconfig/ci.attachconfig.yml @@ -12,3 +12,9 @@ devices.uart: - CONFIG_RT_USING_SERIAL=y - CONFIG_RT_USING_SERIAL_V1=y - CONFIG_BSP_USING_UART=y +devices.spi: + <<: *scons + kconfig: + - CONFIG_RT_USING_SPI=y + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI2=y diff --git a/bsp/ESP/ESP32_C6/README.md b/bsp/ESP/ESP32_C6/README.md index d71000f86e0b..e5c557af2db0 100644 --- a/bsp/ESP/ESP32_C6/README.md +++ b/bsp/ESP/ESP32_C6/README.md @@ -44,7 +44,7 @@ ESP32-C6-DevKitC-1 是乐鑫推出的一款基于 RISC-V 内核的开发板， | IDE/编译器 | 已测试版本 | | ---------- | ---------- | -| GCC | Espressif riscv32-esp-elf GCC 11.2.0 | +| GCC | Espressif riscv32-esp-elf GCC 15.2.0 | ## 3 使用说明 @@ -52,7 +52,7 @@ ESP32-C6-DevKitC-1 是乐鑫推出的一款基于 RISC-V 内核的开发板， ### 3.1 使用 Env 编译 BSP -1. 下载 [riscv32-esp-elf GCC 11.2.0](https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-win64.zip)（Windows）。Linux 用同版本的 `linux-amd64` 包。 +1. 下载 [riscv32-esp-elf GCC 15.2.0](https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-w64-mingw32.zip)（Windows）。Linux 用同版本的 `linux-amd64` 包。 2. 下载 Env 工具 [最新版本](https://github.com/RT-Thread/env-windows/releases) 3. 将 [esp-idf 提交 `4fa003074a73774369d38123749fe64b7b4acbd3`](https://github.com/cms19859230182-lang/esp-idf/commit/4fa003074a73774369d38123749fe64b7b4acbd3)（`bsp/esp32c6-scons`）放到 `packages/ESP-IDF-latest`。官方 `RT-Thread-packages/esp-idf` 里还没有这些 C6 源码，`pkgs --update` 下到的包编不过。SConstruct 发现包里没有 C6 时，拉取的也是这一次提交，不跟分支尖走。 4. 在当前 BSP 目录下执行 `scons --exec-path=工具链的bin目录` diff --git a/bsp/ESP/ESP32_C6/SConstruct b/bsp/ESP/ESP32_C6/SConstruct index 53a6ecdbffae..2d877aebd133 100644 --- a/bsp/ESP/ESP32_C6/SConstruct +++ b/bsp/ESP/ESP32_C6/SConstruct @@ -152,8 +152,8 @@ def _match_idf_spi_lock_stub_to_spi_config(): if spi_selected: marker = b'skip_name = (' if marker not in text: - raise RuntimeError('%s has no %s to skip spi_lock_stub.c in' - % (sc, marker.decode())) + # In ESP-IDF v6.1+, spi_lock_stub is no longer present; spi_common.c is built directly. + return text = text.replace(marker, marker + entry, 1) else: text = text.replace(entry, b'', 1) diff --git a/bsp/ESP/ESP32_C6/docker/Dockerfile b/bsp/ESP/ESP32_C6/docker/Dockerfile index b39f3fa10ec0..3fbb87721df6 100644 --- a/bsp/ESP/ESP32_C6/docker/Dockerfile +++ b/bsp/ESP/ESP32_C6/docker/Dockerfile @@ -15,9 +15,9 @@ RUN apt update && \ USER dev WORKDIR /home/dev -RUN wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz && \ - sudo tar -xf riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz -C /opt && \ - rm riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz +RUN wget -q https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz && \ + sudo tar -xf riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz -C /opt && \ + rm riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz ENV PATH="/opt/riscv32-esp-elf/bin:${PATH}" diff --git a/bsp/ESP/ESP32_C6/idf_port/SConscript b/bsp/ESP/ESP32_C6/idf_port/SConscript index 5da5ca76f011..6eee3b883d1c 100644 --- a/bsp/ESP/ESP32_C6/idf_port/SConscript +++ b/bsp/ESP/ESP32_C6/idf_port/SConscript @@ -16,122 +16,4 @@ CPPPATH = Split( group = DefineGroup('idf_port', src, depend = [''], CPPPATH = CPPPATH) -# bsp/ESP/libraries/drivers/drv_spi.c calls the ESP-IDF master mode SPI driver: -# spi_bus_initialize() lives in components/driver/spi_common.c and -# spi_bus_add_device()/spi_device_acquire_bus()/spi_device_polling_transmit()/ -# spi_device_release_bus() in components/driver/spi_master.c. The package's own -# driver group drops both for C6 (packages/ESP-IDF-latest/SConscript:999 keeps -# only gpio.c, rtc_io.c, uart.c and spi_bus_lock.c out of components/driver), so -# they are compiled here -- and only with BSP_USING_SPI selected, so a default -# build adds nothing. -if GetDepend(['BSP_USING_SPI']): - from env_package import find_package_path - - bsp_root = os.path.normpath(os.path.join(GetCurrentDir(), '..')) - idf = find_package_path(bsp_root, 'ESP-IDF-latest', - relative_to=bsp_root, pathsep='/') - wrapper = find_package_path(bsp_root, 'FreeRTOS-Wrapper-latest', - relative_to=bsp_root, pathsep='/') - - # scons resolves these against the BSP root (the variant dir 'build' mirrors - # them), so '..' steps out of this idf_port directory; the include - # directories below are absolute to stay independent of that. - spi_src = [ - '../%s/components/driver/spi_common.c' % idf, - '../%s/components/driver/spi_master.c' % idf, - # spi_common.c and spi_master.c are written against the HAL layer, and - # this package's C6 hal group drops spi_hal.c; without it the ten - # spi_hal_* calls those two files make have no definition. - '../%s/components/hal/spi_hal.c' % idf, - # spi_common.c reaches GDMA through its own SOC_GDMA_SUPPORTED section - # (soc/esp32c6/include/soc/soc_caps.h defines it as 1), and that code is - # compiled into the object no matter what the third argument of - # spi_bus_initialize() is. The package drops every path containing - # 'gdma' from its C6 source list, so the driver and its hal wrapper are - # compiled here instead. The package's gdma.c is written against the C3 - # generation of hal/gdma_ll.h and that tree is shared with the C3 BSP, - # so this BSP carries its own C6-correct copy (src/gdma.c) instead of - # rewriting the package file at build time. - 'src/gdma.c', - '../%s/components/hal/gdma_hal.c' % idf, - # gdma.c reads gdma_periph_signals (gdma.c:541 and on) to map a - # GDMA_TRIG_PERIPH_* onto the signal slots of a channel; the one object - # file defining it is this SoC table, which the package drops for the - # same 'gdma' reason as the two files above. - '../%s/components/soc/esp32c6/gdma_periph.c' % idf, - # this gcc has no __atomic_compare_exchange_1 (see the file); the byte - # sized compare-exchange of spi_common.c's atomic_bool needs one. - 'src/rt_atomic_cas_stub.c', - ] - - # headers the two files include. freertos/queue.h and freertos/task.h come - # from the RT-Thread FreeRTOS wrapper, like everywhere else in this BSP: the - # kernel copy inside the package wants an IDF sdkconfig this BSP does not - # carry. - spi_path = [os.path.join(bsp_root, idf, 'components', p) for p in ( - 'driver/include', - 'esp_common/include', - 'esp_hw_support/include', - 'esp_hw_support/port/esp32c6/include', - 'esp_rom/include', - 'esp_system/include', - 'esp_system/port/include', - 'esp_system/port/include/private', - 'esp_timer/include', - 'hal/include', - 'hal/esp32c6/include', - 'hal/platform_port/include', - 'heap/include', - 'log/include', - 'newlib/platform_include', - 'riscv/include', - 'soc/include', - 'soc/esp32c6/include', - )] + [os.path.join(bsp_root, wrapper, 'FreeRTOS/include')] - - # hal/esp32c6/include/hal/spi_ll.h names SPI_CLK_SRC_XTAL/SPI_CLK_SRC_RC_FAST - # (enumerators of soc/clk_tree_defs.h) and spi_command_t with its - # SPI_CMD_HD_* values, and this package snapshot defines neither of the - # latter anywhere -- only spi_ll.h uses them, hal/include/hal/spi_types.h has - # no spi_command_t. drv_spi.c carries the declarations for its own - # translation unit; these flags give the package's own sources the same - # thing. The real home of both is the package's hal/include/hal/spi_types.h. - # One string, because building.py appends LOCAL_CFLAGS to a CFLAGS string. - spi_flags = ( - '-include soc/clk_tree_defs.h' - ' -Dspi_command_t=int' - ' -DSPI_CMD_HD_WRBUF=0x01' - ' -DSPI_CMD_HD_RDBUF=0x02' - ' -DSPI_CMD_HD_WRDMA=0x03' - ' -DSPI_CMD_HD_RDDMA=0x04' - ' -DSPI_CMD_HD_SEG_END=0x05' - ' -DSPI_CMD_HD_EN_QPI=0x06' - ' -DSPI_CMD_HD_WR_END=0x07' - ' -DSPI_CMD_HD_INT0=0x08' - ' -DSPI_CMD_HD_INT1=0x09' - ' -DSPI_CMD_HD_INT2=0x0A' - ) - - group += DefineGroup('idf_port_spi', spi_src, depend = ['BSP_USING_SPI'], - LOCAL_CPPPATH = spi_path, LOCAL_CFLAGS = spi_flags) - - # spi_hal.c is only init/deinit/cal_clock. spi_hal_setup_device, - # spi_hal_setup_trans, spi_hal_prepare_data, spi_hal_user_start and - # spi_hal_fetch_result -- everything spi_master.c drives a transfer with -- - # are in spi_hal_iram.c, the second file of that pair, which this package's - # C6 drop_hal list removes as well. - # - # It is a group of its own because it is the only source that may see - # include/spi_ll_master_start_compat.h: that header defines a macro named - # spi_ll_master_user_start, and giving it to spi_common.c, spi_master.c or - # gdma.c would only shadow the C6 header's own helpers in files that never - # ask for that name. - iram_path = [os.path.join(bsp_root, 'idf_port', 'include')] + spi_path - group += DefineGroup('idf_port_spi_iram', - ['../%s/components/hal/spi_hal_iram.c' % idf], - depend = ['BSP_USING_SPI'], - LOCAL_CPPPATH = iram_path, - LOCAL_CFLAGS = spi_flags + - ' -include spi_ll_master_start_compat.h') - Return('group') diff --git a/bsp/ESP/ESP32_C6/idf_port/include/freertos/portmacro.h b/bsp/ESP/ESP32_C6/idf_port/include/freertos/portmacro.h index d602b327312a..270642b3920f 100644 --- a/bsp/ESP/ESP32_C6/idf_port/include/freertos/portmacro.h +++ b/bsp/ESP/ESP32_C6/idf_port/include/freertos/portmacro.h @@ -72,13 +72,13 @@ extern "C" { * - The port types must come first as they are used further down in this file * ------------------------------------------------------------------------------------------------------------------ */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short #define portSTACK_TYPE rt_ubase_t -#define portBASE_TYPE rt_base_t +#define portBASE_TYPE rt_base_t typedef portSTACK_TYPE StackType_t; typedef rt_base_t BaseType_t; @@ -86,6 +86,39 @@ typedef rt_ubase_t UBaseType_t; typedef rt_tick_t TickType_t; #define portMAX_DELAY (TickType_t) RT_TICK_MAX +/* + * FreeRTOS V11 definitions that ESP-IDF v6.1 headers expect but the + * FreeRTOS-Wrapper kernel (FreeRTOS V10.4.6) does not provide. + */ +/* RISC-V has no privilege levels, so the annotation expands to nothing. */ +#ifndef PRIVILEGED_FUNCTION +#define PRIVILEGED_FUNCTION +#endif +/* FreeRTOS V11 renamed nothing here: `StaticList_t` is just an alias of + `struct xLIST`. Used by components/esp_ringbuf/include/freertos/ringbuf.h. */ +#ifndef RT_FREERTOS_WRAPPER_STATIC_LIST_T +#define RT_FREERTOS_WRAPPER_STATIC_LIST_T +#include "freertos/list.h" +typedef List_t StaticList_t; +#endif + +/* + * ESP-IDF v6.1's components/esp_ringbuf blocks on the FreeRTOS task event + * lists, which FreeRTOS V11 provides and FreeRTOS-Wrapper does not. + * components/rtthread/scons/event_list.c implements the two functions below on + * top of the wrapper's list implementation; the declarations have to be visible + * here because esp_ringbuf calls them after a plain . + * vTaskInternalSetTimeOutState() already exists in the wrapper's tasks.c but is + * not declared in its task.h. + */ +void vTaskPlaceOnEventList(List_t *const pxEventList, TickType_t xTicksToWait); +BaseType_t xTaskRemoveFromEventList(List_t *const pxEventList); +/* The wrapper's tasks.c defines this with TimeOut_t, which is a typedef of + `struct xTIME_OUT` in its freertos/task.h. Spell the tag out, because + task.h is not included here and a different tag would be a different type. */ +struct xTIME_OUT; +void vTaskInternalSetTimeOutState(struct xTIME_OUT *const pxTimeOut); + struct rt_semaphore_wrapper { struct rt_semaphore sem; @@ -98,9 +131,9 @@ struct rt_semaphore_wrapper * - Required by FreeRTOS * ------------------------------------------------------------------------------------------------------------------ */ -#define portTICK_PERIOD_MS ((TickType_t)(1000 / configTICK_RATE_HZ)) -#define portBYTE_ALIGNMENT RT_ALIGN_SIZE -#define portNOP() __asm volatile(" nop ") +#define portTICK_PERIOD_MS ((TickType_t) (1000 / configTICK_RATE_HZ)) +#define portBYTE_ALIGNMENT RT_ALIGN_SIZE +#define portNOP() __asm volatile (" nop ") /* ---------------------------------------------- Forward Declarations ------------------------------------------------- @@ -156,22 +189,21 @@ BaseType_t xPortInterruptedFromISRContext(void); * @note Not a true spinlock as single core RISC-V does not have atomic compare and set instruction * @note Keep portMUX_INITIALIZER_UNLOCKED in sync with this struct */ -typedef struct -{ +typedef struct { uint32_t owner; uint32_t count; } portMUX_TYPE; /**< Spinlock initializer */ -#define portMUX_INITIALIZER_UNLOCKED { \ - .owner = portMUX_FREE_VAL, \ - .count = 0, \ -} -#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ -#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ -#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ -#define portMUX_INITIALIZE(mux) ({ \ +#define portMUX_INITIALIZER_UNLOCKED { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ + } +#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ +#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ +#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ +#define portMUX_INITIALIZE(mux) ({ \ (mux)->owner = portMUX_FREE_VAL; \ - (mux)->count = 0; \ + (mux)->count = 0; \ }) // ------------------ Critical Sections -------------------- @@ -199,7 +231,7 @@ void vPortExitCritical(void); * * @note [refactor-todo] The rest of ESP-IDF should call taskYield() instead */ -#define vPortYield(void) rt_thread_yield() +#define vPortYield(void) rt_thread_yield() /** * @brief Checks if the current core can yield @@ -243,9 +275,36 @@ void vPortSetStackWatchpoint(void *pxStackStart); */ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) { - return (BaseType_t)esp_cpu_get_core_id(); + return (BaseType_t) esp_cpu_get_core_id(); } +/* + * The ESP-IDF v6.1 refers to StaticStreamBuffer_t, + * which FreeRTOS V11 defines in its FreeRTOS.h. The FreeRTOS-Wrapper kernel + * is V10.4.6 and provides no stream buffers, so nothing in the RT-Thread + * scons build can allocate one; the type only has to exist for the headers + * to parse. Same layout as ESP-IDF's components/freertos/FreeRTOS-Kernel. + */ +#ifndef RT_FREERTOS_WRAPPER_STATIC_STREAM_BUFFER_T +#define RT_FREERTOS_WRAPPER_STATIC_STREAM_BUFFER_T +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[4]; + void * pvDummy2[3]; + uint8_t ucDummy3; +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; +#endif +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + void * pvDummy5[2]; +#endif + portMUX_TYPE xDummyStreamBufferLock; +} StaticStreamBuffer_t; +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; +#endif + + /* ------------------------------------------- FreeRTOS Porting Interface ---------------------------------------------- * - Contains all the mappings of the macros required by FreeRTOS @@ -255,80 +314,65 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void) // --------------------- Interrupts ------------------------ -#define portDISABLE_INTERRUPTS() vPortEnterCritical() -#define portENABLE_INTERRUPTS() vPortExitCritical() -#define portSET_INTERRUPT_MASK_FROM_ISR() rt_hw_interrupt_disable() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) rt_hw_interrupt_enable(uxSavedStatusValue) +#define portDISABLE_INTERRUPTS() vPortEnterCritical() +#define portENABLE_INTERRUPTS() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() rt_hw_interrupt_disable() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) rt_hw_interrupt_enable(uxSavedStatusValue) // ------------------ Critical Sections -------------------- -#define portENTER_CRITICAL(mux) \ - { \ - (void)mux; \ - vPortEnterCritical(); \ - } -#define portEXIT_CRITICAL(mux) \ - { \ - (void)mux; \ - vPortExitCritical(); \ - } -#define portTRY_ENTER_CRITICAL(mux, timeout) ({ \ - (void)mux; \ - (void)timeout; \ - vPortEnterCritical(); \ - BaseType_t ret = pdPASS; \ - ret; \ +#define portENTER_CRITICAL(mux) {(void)mux; vPortEnterCritical();} +#define portEXIT_CRITICAL(mux) {(void)mux; vPortExitCritical();} +#define portTRY_ENTER_CRITICAL(mux, timeout) ({ \ + (void)mux; (void)timeout; \ + vPortEnterCritical(); \ + BaseType_t ret = pdPASS; \ + ret; \ }) //In single-core RISC-V, we can use the same critical section API -#define portENTER_CRITICAL_ISR(mux) portENTER_CRITICAL(mux) -#define portEXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL(mux) -#define portTRY_ENTER_CRITICAL_ISR(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) +#define portENTER_CRITICAL_ISR(mux) portENTER_CRITICAL(mux) +#define portEXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL(mux) +#define portTRY_ENTER_CRITICAL_ISR(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) /* [refactor-todo] on RISC-V, both ISR and non-ISR cases result in the same call. We can redefine this macro */ -#define portENTER_CRITICAL_SAFE(mux) ({ \ - if (xPortInIsrContext()) \ - { \ - portENTER_CRITICAL_ISR(mux); \ - } \ - else \ - { \ - portENTER_CRITICAL(mux); \ - } \ +#define portENTER_CRITICAL_SAFE(mux) ({ \ + if (xPortInIsrContext()) { \ + portENTER_CRITICAL_ISR(mux); \ + } else { \ + portENTER_CRITICAL(mux); \ + } \ }) -#define portEXIT_CRITICAL_SAFE(mux) ({ \ - if (xPortInIsrContext()) \ - { \ - portEXIT_CRITICAL_ISR(mux); \ - } \ - else \ - { \ - portEXIT_CRITICAL(mux); \ - } \ +#define portEXIT_CRITICAL_SAFE(mux) ({ \ + if (xPortInIsrContext()) { \ + portEXIT_CRITICAL_ISR(mux); \ + } else { \ + portEXIT_CRITICAL(mux); \ + } \ }) -#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) +#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portTRY_ENTER_CRITICAL(mux, timeout) // ---------------------- Yielding ------------------------- -#define portYIELD() rt_thread_yield() -#define portYIELD_FROM_ISR_NO_ARG() rt_thread_yield() +#define portYIELD() rt_thread_yield() +#define portYIELD_FROM_ISR_NO_ARG() rt_thread_yield() #define portYIELD_FROM_ISR_ARG(xHigherPriorityTaskWoken) ({ \ - if (xHigherPriorityTaskWoken == pdTRUE) \ - { \ - rt_thread_yield(); \ - } \ + if (xHigherPriorityTaskWoken == pdTRUE) { \ + rt_thread_yield(); \ + } \ }) /** * @note The macro below could be used when passing a single argument, or without any argument, * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form * might result in undesired behavior */ -#if defined(__cplusplus) && (__cplusplus > 201703L) -#define portYIELD_FROM_ISR(...) CHOOSE_MACRO_VA_ARG(portYIELD_FROM_ISR_ARG, portYIELD_FROM_ISR_NO_ARG __VA_OPT__(, ) __VA_ARGS__)(__VA_ARGS__) +#if defined(__cplusplus) && (__cplusplus > 201703L) +#define portYIELD_FROM_ISR(...) CHOOSE_MACRO_VA_ARG(portYIELD_FROM_ISR_ARG, portYIELD_FROM_ISR_NO_ARG __VA_OPT__(,) __VA_ARGS__)(__VA_ARGS__) #else #define portYIELD_FROM_ISR(...) CHOOSE_MACRO_VA_ARG(portYIELD_FROM_ISR_ARG, portYIELD_FROM_ISR_NO_ARG, ##__VA_ARGS__)(__VA_ARGS__) #endif + /* --------------------------------------------- Inline Implementations ------------------------------------------------ * - Implementation of inline functions of the forward declares * - Should come after forward declare and FreeRTOS Porting interface, as implementation may use both. @@ -345,12 +389,12 @@ FORCE_INLINE_ATTR bool xPortCanYield(void) return (level == 0); } -#define FREERTOS_PRIORITY_TO_RTTHREAD(priority) (configMAX_PRIORITIES - 1 - (priority)) -#define RTTHREAD_PRIORITY_TO_FREERTOS(priority) (RT_THREAD_PRIORITY_MAX - 1 - (priority)) +#define FREERTOS_PRIORITY_TO_RTTHREAD(priority) ( configMAX_PRIORITIES - 1 - ( priority ) ) +#define RTTHREAD_PRIORITY_TO_FREERTOS(priority) ( RT_THREAD_PRIORITY_MAX - 1 - ( priority ) ) /* Use this macro to calculate the buffer size when allocating a queue statically * To ensure the buffer can fit the desired number of messages */ -#define QUEUE_BUFFER_SIZE(uxQueueLength, uxItemSize) ((RT_ALIGN(uxItemSize, RT_ALIGN_SIZE) + sizeof(void *)) * uxQueueLength) +#define QUEUE_BUFFER_SIZE( uxQueueLength, uxItemSize ) ( ( RT_ALIGN( uxItemSize, RT_ALIGN_SIZE ) + sizeof( void * ) ) * uxQueueLength ) BaseType_t rt_err_to_freertos(rt_err_t rt_err); diff --git a/bsp/ESP/ESP32_C6/idf_port/ld/sections.ld b/bsp/ESP/ESP32_C6/idf_port/ld/sections.ld index 69bd53df9d36..3e51278ff1be 100644 --- a/bsp/ESP/ESP32_C6/idf_port/ld/sections.ld +++ b/bsp/ESP/ESP32_C6/idf_port/ld/sections.ld @@ -147,6 +147,8 @@ SECTIONS _iram_start = ABSOLUTE(.); /* Vectors go to start of IRAM */ ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); + _vector_table_start = ABSOLUTE(.); + KEEP(*(.exception_vectors_table.text)); KEEP(*(.exception_vectors.text)); . = ALIGN(4); @@ -386,8 +388,17 @@ SECTIONS soc_reserved_memory_region_end = ABSOLUTE(.); /* System init functions registered via ESP_SYSTEM_INIT_FN */ _esp_system_init_fn_array_start = ABSOLUTE(.); + _esp_sys_init_fn_start = ABSOLUTE(.); KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_sys_init_fn.*))) _esp_system_init_fn_array_end = ABSOLUTE(.); + _esp_sys_init_fn_end = ABSOLUTE(.); + + . = ALIGN(4); + _esp_libc_clock_array_start = ABSOLUTE(.); + KEEP (*(.esp_libc_clock_desc)) + _esp_libc_clock_array_end = ABSOLUTE(.); + /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))); diff --git a/bsp/ESP/ESP32_C6/idf_port/src/port.c b/bsp/ESP/ESP32_C6/idf_port/src/port.c index e256ae095b21..d5dea544cb91 100644 --- a/bsp/ESP/ESP32_C6/idf_port/src/port.c +++ b/bsp/ESP/ESP32_C6/idf_port/src/port.c @@ -44,7 +44,6 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_attr.h" diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/Kconfig b/bsp/ESP/ESP32_C6/libraries/drivers/Kconfig new file mode 100644 index 000000000000..4cbbcddd917d --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/Kconfig @@ -0,0 +1,220 @@ + +config SOC_ESPRESSIF + bool + +choice + prompt "Espressif SoC" + default SOC_ESP32_C3 + +config SOC_ESP32_C3 + bool "ESP32-C3" + select SOC_ESPRESSIF + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select PKG_USING_ESP_IDF + select PKG_USING_FREERTOS_WRAPPER + select PKG_FREERTOS_USING_CONFIG_H + +config SOC_ESP32_C6 + bool "ESP32-C6" + select SOC_ESPRESSIF + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select PKG_USING_ESP_IDF + select PKG_USING_FREERTOS_WRAPPER + select PKG_FREERTOS_USING_CONFIG_H +endchoice + +menu "Hardware Drivers Config" + +choice BSP_BOARD_SEL + prompt "Select BSP board " + default BSP_BOARD_ESP32C6_DEVKITC1 if SOC_ESP32_C6 + default BSP_BOARD_LUATOS_ESP32C3 + + config BSP_BOARD_LUATOS_ESP32C3 + bool "LUATOS ESP32C3 board" + depends on SOC_ESP32_C3 + + config BSP_BOARD_HX_EXP32C3 + bool "HONGXU ESP32C3 board" + depends on SOC_ESP32_C3 + + config BSP_BOARD_ESP32C6_DEVKITC1 + bool "ESP32-C6-DevKitC-1" + depends on SOC_ESP32_C6 +endchoice + +menu "Onboard Peripheral Drivers" + config RT_BSP_LED_PIN + int "LED GPIO PIN SET" + default 12 if BSP_BOARD_LUATOS_ESP32C3 + default 8 if BSP_BOARD_HX_EXP32C3 + depends on BSP_USING_GPIO && !BSP_BOARD_ESP32C6_DEVKITC1 + + config RT_BSP_UART_PORT + int "UART PORT SET" + default 0 + depends on BSP_USING_UART + + config RT_BSP_UART_TX_PIN + int "UART TX PIN SET" + default 21 if BSP_BOARD_LUATOS_ESP32C3 + default 16 if BSP_BOARD_ESP32C6_DEVKITC1 + depends on BSP_USING_UART + + config RT_BSP_UART_RX_PIN + int "UART RX PIN SET" + default 20 if BSP_BOARD_LUATOS_ESP32C3 + default 17 if BSP_BOARD_ESP32C6_DEVKITC1 + depends on BSP_USING_UART + + config RT_BSP_SPI_CS_PIN + int "SPI GPIO PIN SET" + default 10 if BSP_BOARD_LUATOS_ESP32C3 + depends on BSP_USING_SPI2 + +endmenu + + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_UART + bool "Enable UART" + select RT_USING_SERIAL + select RT_USING_SERIAL_V1 + default y + + menuconfig BSP_USING_I2C + bool "Enable I2C" + depends on SOC_ESP32_C3 + default n + select RT_USING_I2C + if BSP_USING_I2C + menuconfig BSP_USING_HW_I2C + bool "Enable HardWare I2C" + default n + menuconfig BSP_USING_SOFT_I2C + bool "Enable software I2C (swi2c)" + default n + select RT_USING_I2C + select RT_USING_SOFT_I2C + if BSP_USING_SOFT_I2C + menuconfig BSP_USING_SOFT_I2C0 + bool "Enable software I2C0 Bus (swi2c0)" + default n + select RT_USING_SOFT_I2C0 + if BSP_USING_SOFT_I2C0 + config RT_SOFT_I2C0_SCL_PIN + int "swi2c0 SCL pin number" + default 19 + config RT_SOFT_I2C0_SDA_PIN + int "swi2c0 SDA pin number" + default 18 + endif + endif + + + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + depends on SOC_ESP32_C3 || SOC_ESP32_C6 + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + endif + + config BSP_USING_WIFI + bool "Enable WIFI" + depends on SOC_ESP32_C3 + select RT_USING_WIFI + default n + + config BSP_USING_BLE + bool "Enable BLE" + depends on SOC_ESP32_C3 + default n + + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" + depends on SOC_ESP32_C3 + select RT_USING_CLOCK_TIME + default n + if BSP_USING_CLOCK_TIMER + config BSP_USING_TIMER0 + bool "Enable CLOCK_TIMER0" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + depends on SOC_ESP32_C3 || SOC_ESP32_C6 + default y if SOC_ESP32_C6 + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default y if SOC_ESP32_C6 + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + depends on SOC_ESP32_C3 + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM0 + bool "Enable PWM0" + default n + if BSP_USING_PWM0 + config BSP_LEDC_CH0_GPIO + int "LEDC CH0 GPIO PIN SET" + default 12 + config BSP_LEDC_CH1_GPIO + int "LEDC CH1 GPIO PIN SET" + default 6 + config BSP_LEDC_CH2_GPIO + int "LEDC CH2 GPIO PIN SET" + default 2 + config BSP_LEDC_CH3_GPIO + int "LEDC CH3 GPIO PIN SET" + default 10 + config BSP_LEDC_CH4_GPIO + int "LEDC CH4 GPIO PIN SET" + default 8 + config BSP_LEDC_CH5_GPIO + int "LEDC CH5 GPIO PIN SET" + default 18 + endif + endif + +endmenu + +config BSP_ENABLE_GDBSTUB + bool "Enable ESP_GDBSTUB compontent" + depends on SOC_ESPRESSIF + default n + + config RT_SOFT_I2C0_HAS_PIN_DEFAULT + bool + default y if RT_USING_SOFT_I2C0 + + config RT_SOFT_I2C0_SCL_PIN_DEFAULT + int + default 19 if RT_USING_SOFT_I2C0 + + config RT_SOFT_I2C0_SDA_PIN_DEFAULT + int + default 18 if RT_USING_SOFT_I2C0 + +endmenu diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/SConscript b/bsp/ESP/ESP32_C6/libraries/drivers/SConscript new file mode 100644 index 000000000000..7128e5285326 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/SConscript @@ -0,0 +1,39 @@ +import os +from building import * + +cwd = GetCurrentDir() +src = ['board.c'] + +# This directory is built through a scons variant dir (duplicate=0), so the +# hand maintained sdkconfig.h that the ESP-IDF sources include is not copied +# next to the objects. Add the real directory to the include path. +CPPPATH = [cwd, Dir('.').srcnode().abspath] + +if GetDepend('BSP_USING_GPIO'): + src += ['drv_gpio.c'] + +if GetDepend('BSP_USING_UART'): + src += ['drv_uart.c'] + +if GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('BSP_USING_I2C'): + src += ['drv_hw_i2c.c'] + +if GetDepend('BSP_USING_PWM'): + src += ['drv_pwm.c'] + +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] + +if GetDepend('BSP_USING_WIFI'): + src += ['drv_wifi.c'] + +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] + + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/board.c b/bsp/ESP/ESP32_C6/libraries/drivers/board.c new file mode 100644 index 000000000000..8ad631d593c7 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/board.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-02 supperthomas first version + * 2024-12-08 wumingzi support rt_hw_us_delay + */ + +#include +#include "rttypes.h" +#include "hal/systimer_hal.h" +#include "hal/systimer_ll.h" +#include "esp_private/panic_internal.h" +#include "esp_private/systimer.h" +#include "esp_private/periph_ctrl.h" +#include "esp_intr_alloc.h" +#include "esp_attr.h" +#include "esp_timer.h" +#include "driver/gptimer.h" + +/* CI pulls RT-Thread-packages/esp-idf rtt-dev, where OS-tick IDs live only as SYSTIMER_LL_*. + * IDF v6.1 / package PR #18 reintroduces the non-LL names in esp_private/systimer.h. */ +#ifndef SYSTIMER_COUNTER_OS_TICK +#define SYSTIMER_COUNTER_OS_TICK SYSTIMER_LL_COUNTER_OS_TICK +#endif +#ifndef SYSTIMER_ALARM_OS_TICK_CORE0 +#define SYSTIMER_ALARM_OS_TICK_CORE0 SYSTIMER_LL_ALARM_OS_TICK_CORE0 +#endif + +static systimer_hal_context_t systimer_hal; +IRAM_ATTR void rt_SysTickIsrHandler(void *arg) +{ + systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0); + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_systick_init(void) +{ + esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LEVEL1, rt_SysTickIsrHandler, &systimer_hal, NULL); + periph_module_enable(PERIPH_SYSTIMER_MODULE); + systimer_hal_init(&systimer_hal); + systimer_hal_tick_rate_ops_t ops = { + .ticks_to_us = systimer_ticks_to_us, + .us_to_ticks = systimer_us_to_ticks, + }; + systimer_hal_set_tick_rate_ops(&systimer_hal, &ops); + systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_COUNTER_OS_TICK, 0); + systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_COUNTER_OS_TICK); + systimer_hal_connect_alarm_counter(&systimer_hal, SYSTIMER_ALARM_OS_TICK_CORE0, SYSTIMER_COUNTER_OS_TICK); + systimer_hal_set_alarm_period(&systimer_hal, SYSTIMER_ALARM_OS_TICK_CORE0, 1000000UL / RT_TICK_PER_SECOND); + systimer_hal_select_alarm_mode(&systimer_hal, SYSTIMER_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_PERIOD); + systimer_hal_counter_can_stall_by_cpu(&systimer_hal, 1, 0, true); + systimer_hal_enable_alarm_int(&systimer_hal, SYSTIMER_ALARM_OS_TICK_CORE0); + systimer_hal_enable_counter(&systimer_hal, SYSTIMER_COUNTER_OS_TICK); +} + +#ifdef SOC_ESP32_C6 +#include "riscv/csr.h" + +static void c6_reserve_broken_intr(void) +{ + /* CPU lines 3 and 4 do not latch an enable on this chip. Reserve them + * before esp_intr_alloc so the chosen line, its non-IRAM mask and the + * matrix route are written together. Copying the handler afterwards + * leaves non_iram_int_mask on the old line. */ + ESP_ERROR_CHECK(esp_intr_reserve(3, 0)); + ESP_ERROR_CHECK(esp_intr_reserve(4, 0)); +} +#endif + +void rt_hw_board_init(void) +{ +#ifdef SOC_ESP32_C6 + RV_WRITE_CSR(mideleg, 0); + c6_reserve_broken_intr(); +#endif + rt_hw_systick_init(); + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +#ifdef SOC_ESP32_C6 +#include "esp_rom_sys.h" + +void rt_hw_us_delay(rt_uint32_t us) +{ + esp_rom_delay_us(us); +} +#else +static gptimer_handle_t gptimer_hw_us = NULL; + +static int delay_us_init(void) +{ + gptimer_config_t timer_config = { + .clk_src = GPTIMER_CLK_SRC_DEFAULT, + .direction = GPTIMER_COUNT_UP, + .resolution_hz = 1 * 1000 * 1000, /* 1MHz, 1 tick = 1us*/ + }; + ESP_ERROR_CHECK(gptimer_new_timer(&timer_config, &gptimer_hw_us)); + ESP_ERROR_CHECK(gptimer_enable(gptimer_hw_us)); + return RT_EOK; +} +INIT_DEVICE_EXPORT(delay_us_init); + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint64_t count = 0; + ESP_ERROR_CHECK(gptimer_start(gptimer_hw_us)); + ESP_ERROR_CHECK(gptimer_set_raw_count(gptimer_hw_us, 0)); + /* Retrieve the timestamp at anytime*/ + while (count < (uint64_t)us) + { + ESP_ERROR_CHECK(gptimer_get_raw_count(gptimer_hw_us, &count)); + } + ESP_ERROR_CHECK(gptimer_stop(gptimer_hw_us)); +} +#endif diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/board.h b/bsp/ESP/ESP32_C6/libraries/drivers/board.h new file mode 100644 index 000000000000..2e3a166145bf --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/board.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-02 supperthomas first version + * 2024-12-08 wumingzi support rt_hw_us_delay + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "rttypes.h" + +#ifdef __cplusplus +extern "C" { +#endif +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.c new file mode 100644 index 000000000000..05dd73958d29 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-23 Chushicheng first version + */ + +#include +#include +#include "drv_adc.h" +#include "hal/adc_types.h" + +/* ESP-IDF v6.1 removed the C6 register-level ADC path this driver used on + * 5.1 (PERIPH_SARADC_MODULE, the PCR/APB_SARADC register structs). The + * esp_adc component's adc_oneshot API is available for the C6 in 6.1, so + * route both SoCs through it there and keep the legacy path only for a + * pre-6.1 C6 build. */ +#include "esp_idf_version.h" +#if defined(SOC_ESP32_C6) && (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(6, 0, 0)) +#define ADC_C6_LEGACY_REGACCESS 1 +#endif + +#ifdef ADC_C6_LEGACY_REGACCESS +#include "soc/apb_saradc_struct.h" +#include "soc/pcr_struct.h" +#include "soc/adc_channel.h" +#include "driver/gpio.h" +#include "driver/rtc_io.h" +#include "esp_rom_sys.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/sar_periph_ctrl.h" +#else +#include "esp_adc/adc_oneshot.h" +#endif + +/* ESP-IDF v6.1 renamed the maximum attenuation for the ESP32-C3 from + * 11 dB to 12 dB (ADC_ATTEN_DB_11 -> ADC_ATTEN_DB_12). Both are enum + * constants, so the preprocessor cannot tell them apart with #ifdef; use the + * IDF version macro to keep 5.1 builds working. */ +#include "esp_idf_version.h" +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(6, 0, 0) +#define ADC_DEV_ATTEN ADC_ATTEN_DB_12 +#else +#define ADC_DEV_ATTEN ADC_ATTEN_DB_11 +#endif + +#ifdef BSP_USING_ADC +#define DBG_TAG "drv.adc" +#define DBG_LVL DBG_INFO +#include + +#define EXAMPLE_READ_LEN 256 +#define GET_UNIT(x) ((x >> 3) & 0x1) + +/* esp i2c dirver class */ +struct esp_adc +{ + struct rt_adc_ops ops; + struct rt_adc_device adc_device; + rt_uint8_t adc_id; +#ifndef ADC_C6_LEGACY_REGACCESS + adc_oneshot_unit_handle_t handle; + /* Bit mask of the channels rt_adc_enable() has opened. IDF allows one + * handle per hardware unit, so the unit is created with the first + * channel and released again with the last one. */ + rt_uint8_t channel_enabled; +#endif +}; + +static struct esp_adc_config adc_config[] = { +#ifdef BSP_USING_ADC1 + { + .adc_id = ADC_UNIT_1, + .device_name = "adc1", + }, +#endif +}; + +static struct esp_adc esp_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]; + +static struct rt_mutex adc_lock; + +static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ +#ifdef ADC_C6_LEGACY_REGACCESS + static int adc_on; + int gpio; + + if (channel < 0 || channel > 6) + { + return -RT_EINVAL; + } + if (rt_mutex_take(&adc_lock, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_ERROR; + } + gpio = channel; + if (!enabled) + { + if (adc_on > 0) + { + adc_on--; + sar_periph_ctrl_adc_oneshot_power_release(); + periph_module_disable(PERIPH_SARADC_MODULE); + } + rt_mutex_release(&adc_lock); + return RT_EOK; + } + + periph_module_enable(PERIPH_SARADC_MODULE); + sar_periph_ctrl_adc_oneshot_power_acquire(); + adc_on++; + + PCR.saradc_conf.saradc_clk_en = 1; + PCR.saradc_conf.saradc_rst_en = 0; + PCR.saradc_clkm_conf.saradc_clkm_en = 1; + PCR.saradc_clkm_conf.saradc_clkm_sel = 0; + PCR.saradc_clkm_conf.saradc_clkm_div_num = 15; + PCR.saradc_clkm_conf.saradc_clkm_div_a = 0; + PCR.saradc_clkm_conf.saradc_clkm_div_b = 1; + + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_div = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; + + gpio_config_t cfg = { + .pin_bit_mask = 1ULL << gpio, + .mode = GPIO_MODE_DISABLE, + .pull_up_en = GPIO_PULLUP_DISABLE, + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .intr_type = GPIO_INTR_DISABLE, + }; + gpio_config(&cfg); + rtc_gpio_init(gpio); + rtc_gpio_set_direction(gpio, RTC_GPIO_MODE_DISABLED); + rtc_gpio_pulldown_dis(gpio); + rtc_gpio_pullup_dis(gpio); + + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = 3; + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = channel; + rt_mutex_release(&adc_lock); + return RT_EOK; +#else + struct esp_adc *_adc = rt_container_of(device, struct esp_adc, adc_device); + + if (channel < 0 || channel > 6) + { + return -RT_EINVAL; + } + if (rt_mutex_take(&adc_lock, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_ERROR; + } + + if (enabled) + { + //-------------ADC Init---------------// + /* One handle per hardware unit: a second adc_oneshot_new_unit() for a + * unit that already exists fails with ESP_ERR_NOT_FOUND, so the unit + * is opened with the first channel and shared by the ones after it. */ + if (_adc->channel_enabled == 0) + { + adc_oneshot_unit_init_cfg_t init_config = { + .unit_id = _adc->adc_id, + }; + ESP_ERROR_CHECK(adc_oneshot_new_unit(&init_config, &_adc->handle)); + } + //-------------ADC Config---------------// + adc_oneshot_chan_cfg_t config = { + .bitwidth = ADC_BITWIDTH_DEFAULT, + .atten = ADC_DEV_ATTEN, + }; + ESP_ERROR_CHECK(adc_oneshot_config_channel(_adc->handle, channel, &config)); + _adc->channel_enabled |= (rt_uint8_t)(1u << channel); + } + else + { + _adc->channel_enabled &= (rt_uint8_t) ~(1u << channel); + if (_adc->channel_enabled == 0) + { + ESP_ERROR_CHECK(adc_oneshot_del_unit(_adc->handle)); + } + } + + rt_mutex_release(&adc_lock); + return RT_EOK; +#endif +} + +static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + +#ifdef ADC_C6_LEGACY_REGACCESS + int i; + int done = 0; + uint32_t raw_pin = 0; + rt_err_t result; + + if (rt_mutex_take(&adc_lock, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_ERROR; + } + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = channel; + APB_SARADC.saradc_int_clr.saradc_apb_saradc1_done_int_clr = 1; + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = 0; + esp_rom_delay_us(5); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = 1; + for (i = 0; i < 1000; i++) + { + if (APB_SARADC.saradc_int_raw.saradc_apb_saradc1_done_int_raw) + { + done = 1; + break; + } + esp_rom_delay_us(2); + } + if (done) + { + raw_pin = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; + } + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = 0; + if (!done) + { + result = -RT_ETIMEOUT; + } + else + { + *value = raw_pin; + result = RT_EOK; + } + rt_mutex_release(&adc_lock); + return result; +#else + rt_uint32_t adc_raw = 0; + struct esp_adc *_adc = rt_container_of(device, struct esp_adc, adc_device); + + if (rt_mutex_take(&adc_lock, RT_WAITING_FOREVER) != RT_EOK) + { + return -RT_ERROR; + } + ESP_ERROR_CHECK(adc_oneshot_read(_adc->handle, channel, &adc_raw)); + rt_mutex_release(&adc_lock); + + /* Raw counts, the unit rt_adc_read() has always returned on this BSP: + * documentation/6.components/device-driver/adc/adc.md shows the caller + * converting them to a voltage itself. */ + *value = adc_raw; + + return RT_EOK; +#endif +} + +static const struct rt_adc_ops esp_adc_ops = { + .enabled = _adc_enabled, + .convert = _adc_get_value, + .get_resolution = RT_NULL, + .get_vref = RT_NULL, +}; + +int rt_hw_adc_init(void) +{ + int result = RT_EOK; + + if (rt_mutex_init(&adc_lock, "adc", RT_IPC_FLAG_PRIO) != RT_EOK) + { + return -RT_ERROR; + } + + for (rt_size_t i = 0; i < sizeof(esp_adc_obj) / sizeof(struct esp_adc); i++) + { + esp_adc_obj[i].adc_id = adc_config[i].adc_id; + /* register ADC device */ + if (rt_hw_adc_register(&esp_adc_obj[i].adc_device, adc_config[i].device_name, &esp_adc_ops, &adc_config[i]) == RT_EOK) + { + LOG_D("%s init success", adc_config[i].device_name); + } + else + { + LOG_E("%s register failed", adc_config[i].device_name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif /* BSP_USING_ADC */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.h new file mode 100644 index 000000000000..188af73b1c8f --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_adc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-23 Chushicheng first version + */ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include + +#if defined BSP_USING_ADC + +/* esp config class */ +static struct esp_adc_config +{ + rt_uint8_t adc_id; + const char *device_name; +}; + +int rt_hw_adc_init(void); + +#endif /* BSP_USING_ADC */ +#endif /* __DRV_ADC_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.c new file mode 100644 index 000000000000..a43f5383edf1 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2021-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-03 supperthomas first version + * 2024-12-08 wumingzi support open drain mode for soft i2c + */ + +#include +#include +#include "driver/gpio.h" + +#ifdef RT_USING_PIN + +static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + gpio_set_level(pin, value); + /*TODO:set gpio out put mode */ +} + +static rt_ssize_t mcu_pin_read(rt_device_t dev, rt_base_t pin) +{ + rt_ssize_t value; + value = gpio_get_level(pin); + return value; +} + +static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + gpio_config_t io_conf; + io_conf.intr_type = GPIO_INTR_DISABLE; + io_conf.mode = GPIO_MODE_OUTPUT; + io_conf.pin_bit_mask = (1ULL << pin); + io_conf.pull_down_en = 0; + io_conf.pull_up_en = 0; + gpio_config(&io_conf); + switch (mode) + { + case PIN_MODE_INPUT: + gpio_set_direction(pin, GPIO_MODE_INPUT); + break; + case PIN_MODE_OUTPUT: + gpio_set_direction(pin, GPIO_MODE_OUTPUT); + break; + case PIN_MODE_OUTPUT_OD: + gpio_set_direction(pin, GPIO_MODE_INPUT_OUTPUT_OD); + break; + default: + break; + } + /*TODO:set gpio out put mode */ +} + + +static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t irq_mode, void (*hdr)(void *args), void *args) +{ + /*TODO: start irq handle */ + return -RT_ENOSYS; +} + +static rt_err_t mcu_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + /*TODO:disable gpio irq handle */ + return RT_EOK; +} + +static rt_err_t mcu_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + /*TODO:start irq handle */ + return RT_EOK; +} + +const static struct rt_pin_ops _mcu_pin_ops = { + mcu_pin_mode, + mcu_pin_write, + mcu_pin_read, + mcu_pin_attach_irq, + mcu_pin_detach_irq, + mcu_pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + /*TODO: INIT THE GPIO CLOCK AND OTHER */ + return rt_device_pin_register("pin", &_mcu_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.h new file mode 100644 index 000000000000..d2f4947ce00f --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_gpio.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2021-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-03 supperthomas first version + * + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include + +#ifdef RT_USING_PIN +int rt_hw_pin_init(void); +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.c new file mode 100644 index 000000000000..a690f5596488 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + *2023-03-28 Zxy first version + */ + +#include "drv_hw_i2c.h" +#include "driver/i2c.h"//bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/i2c.h +#include "hal/i2c_types.h"//bsp/ESP32_C3/packages/ESP-IDF-latest/tools/mocks/hal/include/hal/i2c_types.h +#include "esp_err.h" +//#include "portmacro.h"//bsp/ESP32_C3/packages/FreeRTOS_Wrapper-latest/FreeRTOS/portable/rt-thread/portmacro.h +#ifdef BSP_USING_HW_I2C +struct esp32_i2c +{ + struct rt_i2c_bus_device bus; + + i2c_config_t *base; + + char *device_name; +}; + +// #if defined(BSP_USING_I2C0) +static struct esp32_i2c i2c0 = { 0 }; +// #endif + +static rt_size_t _master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + i2c_cmd_handle_t cmd;//创建流程 + rt_size_t ret = (0); + rt_uint32_t index = 0; + // struct esp32_i2c *esp32_i2c = RT_NULL; + struct rt_i2c_msg *msg = RT_NULL; + i2c_rw_t direction;//w-0 r-1 + esp_err_t result = ESP_OK; + + RT_ASSERT(bus != RT_NULL); + + // esp32_i2c = (struct esp32_i2c *)bus; + + for (index = 0; index < num; index++) + { + msg = &msgs[index]; + direction = ((msg->flags & RT_I2C_RD) ? I2C_MASTER_READ : I2C_MASTER_WRITE); + + if (!(msg->flags & RT_I2C_NO_START)) + { + /* Start condition and slave address. */ + cmd = i2c_cmd_link_create();//创建流程 + i2c_master_start(cmd);//启动流程录入 + result = i2c_master_write_byte(cmd, msg->addr << 1 | WRITE_BIT, ACK_CHECK_EN);//发送起始信号和从设备地址 + i2c_master_stop(cmd);//流程录入完毕 + ret = i2c_master_cmd_begin(I2C_NUMBER(0), cmd, 1000 / portTICK_PERIOD_MS);//执行流程 + i2c_cmd_link_delete(cmd);//删除流程任务 + if (ret != ESP_OK) + { + return ret; + } + } + + if (result == ESP_OK) + { + if (direction == I2C_MASTER_WRITE) + { + /* Transmit data. */ + cmd = i2c_cmd_link_create();//创建流程 + i2c_master_start(cmd);//启动流程录入 + result = i2c_master_write_byte(cmd, msg->buf, ACK_CHECK_EN); + i2c_master_stop(cmd);//流程录入完毕 + ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);//执行流程 + i2c_cmd_link_delete(cmd);//删除流程任务 + } + else + { + /* Receive Data. */ + cmd = i2c_cmd_link_create();//创建流程 + i2c_master_start(cmd);//启动流程录入 + result = i2c_master_read_byte(cmd, msg->buf, ACK_VAL); + i2c_master_stop(cmd);//流程录入完毕 + ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);//执行流程 + i2c_cmd_link_delete(cmd);//删除流程任务 + } + } + } + + if (result == ESP_OK) + { + ret = index; + } + + return ret; +} + +static rt_size_t _slave_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + return -RT_ENOSYS; +} + +static rt_err_t _i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args) +{ + return -RT_EINVAL; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = { + _master_xfer, + _slave_xfer, + _i2c_bus_control, +}; + +int rt_hw_i2c_init(void) +{ + i2c0.base = &i2c0; + i2c0.device_name = "i2c0"; + i2c0.bus.ops = &i2c_ops; + int i2c_master_port = I2C_MASTER_NUM;//iic0 + i2c_config_t conf = { + .mode = I2C_MODE_MASTER, + .sda_io_num = I2C_MASTER_SDA_IO, + .sda_pullup_en = GPIO_PULLUP_ENABLE, + .scl_io_num = I2C_MASTER_SCL_IO, + .scl_pullup_en = GPIO_PULLUP_ENABLE, + .master.clk_speed = 100000, + // .clk_flags = 0, /*!< Optional, you can use I2C_SCLK_SRC_FLAG_* flags to choose i2c source clock here. */ + }; + + i2c_param_config(i2c_master_port, &conf);//配置完成 + i2c_driver_install(i2c_master_port, conf.mode, 0, 0, 0);// I2C 设备的初始化 + rt_i2c_bus_device_register(&i2c0.bus, i2c0.device_name); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); +#endif /* RT_USING_I2C */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.h new file mode 100644 index 000000000000..2b87b9737aa5 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_hw_i2c.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + *2023-03-28 Zxy first version + */ +#ifndef __DRV_HW_I2C_H__ +#define __DRV_HW_I2C_H__ + +#include +#include +#include "sdkconfig.h" + +#define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */ +#define READ_BIT I2C_MASTER_READ /*!< I2C master read */ +#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/ +#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */ +#define ACK_VAL 0x0 /*!< I2C ack value */ +#define NACK_VAL 0x1 /*!< I2C nack value */ +#define _I2C_NUMBER(num) I2C_NUM_##num +#define I2C_NUMBER(num) _I2C_NUMBER(num) +#define I2C_MASTER_NUM I2C_NUMBER(0) /*!< I2C port number for master dev */ +#define I2C_MASTER_SCL_IO CONFIG_I2C_MASTER_SCL /*!< gpio number for I2C master clock */ +#define I2C_MASTER_SDA_IO CONFIG_I2C_MASTER_SDA /*!< gpio number for I2C master data */ +#define CONFIG_I2C_MASTER_SCL 6 +#define CONFIG_I2C_MASTER_SDA 5 +int rt_hw_i2c_init(void); + +#endif /* __DRV_HW_I2C_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.c new file mode 100644 index 000000000000..ea33782168c3 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-26 ChuShicheng first version + */ + +#include +#include "drv_pwm.h" +#include "driver/ledc.h" + + +#ifdef BSP_USING_PWM + +#define DBG_LEVEL DBG_LOG +#include +#define LOG_TAG "DRV.PWM" + +#define LEDC_MODE LEDC_LOW_SPEED_MODE +#define LEDC_DUTY_DEFAULT (4095) // Set duty to 50%. ((2 ** 13) - 1) * 50% = 4095 +#define LEDC_FREQUENCY_DEFAULT (5000) // Frequency in Hertz. Set frequency at 5 kHz + +struct esp_pwm +{ + struct rt_device_pwm pwm_device; + rt_uint8_t timer_num; + char *name; +}; + +static struct esp_pwm esp_pwm_obj[] = { +#ifdef BSP_USING_PWM0 + { + .name = "pwm0", + .timer_num = 0, + } +#endif /* BSP_USING_PWM0 */ +}; + +static rt_err_t _pwm_set(struct esp_pwm *obj, struct rt_pwm_configuration *configuration) +{ + float period = configuration->period; + float pulse = configuration->pulse; + float duty = 8191 * (pulse / period); // ((2 ** 13) - 1) * (pulse / period_hz) + float period_hz = 1000000000 / configuration->period; + + ledc_timer_config_t ledc_timer = { + .speed_mode = LEDC_MODE, + .timer_num = obj->timer_num, + .duty_resolution = LEDC_TIMER_13_BIT, + .freq_hz = (uint32_t)period_hz, // Set output frequency at 5 kHz + .clk_cfg = LEDC_AUTO_CLK + }; + ESP_ERROR_CHECK(ledc_timer_config(&ledc_timer)); + + ESP_ERROR_CHECK(ledc_set_duty(LEDC_MODE, configuration->channel, (uint32_t)duty)); + // Update duty to apply the new value + ESP_ERROR_CHECK(ledc_update_duty(LEDC_MODE, configuration->channel)); + + return RT_EOK; +} + +static rt_err_t _pwm_get(struct esp_pwm *obj, struct rt_pwm_configuration *configuration) +{ + uint32_t period_hz = ledc_get_freq(LEDC_MODE, obj->timer_num); + LOG_W("period_hz:%d", period_hz); + uint32_t duty = ledc_get_duty(LEDC_MODE, configuration->channel); + LOG_W("duty:%d", duty); + + configuration->period = 1000000000 / period_hz; + configuration->pulse = duty * configuration->period / 8191; + LOG_W("pulse:%d", configuration->pulse); + + return RT_EOK; +} + +static void pwm_enabled(struct esp_pwm *obj, struct rt_pwm_configuration *configuration, rt_uint8_t enable) +{ + if (enable) + { + ledc_timer_config_t ledc_timer = { + .speed_mode = LEDC_MODE, + .timer_num = obj->timer_num, + .duty_resolution = LEDC_TIMER_13_BIT, + .freq_hz = LEDC_FREQUENCY_DEFAULT, // Set output frequency at 5 kHz + .clk_cfg = LEDC_AUTO_CLK + }; + ESP_ERROR_CHECK(ledc_timer_config(&ledc_timer)); + + // Prepare and then apply the LEDC PWM channel configuration + ledc_channel_config_t ledc_channel = { + .speed_mode = LEDC_MODE, + .channel = configuration->channel, + .timer_sel = obj->timer_num, + .intr_type = LEDC_INTR_DISABLE, + .duty = LEDC_DUTY_DEFAULT, // ((2 ** 13) - 1) * (pulse / period_hz) + .hpoint = 0 + }; + switch (configuration->channel) + { + case LEDC_CHANNEL_0: + ledc_channel.gpio_num = BSP_LEDC_CH0_GPIO; + break; + case LEDC_CHANNEL_1: + ledc_channel.gpio_num = BSP_LEDC_CH1_GPIO; + break; + case LEDC_CHANNEL_2: + ledc_channel.gpio_num = BSP_LEDC_CH2_GPIO; + break; + case LEDC_CHANNEL_3: + ledc_channel.gpio_num = BSP_LEDC_CH3_GPIO; + break; + case LEDC_CHANNEL_4: + ledc_channel.gpio_num = BSP_LEDC_CH4_GPIO; + break; + case LEDC_CHANNEL_5: + ledc_channel.gpio_num = BSP_LEDC_CH5_GPIO; + break; + default: + break; + } + ESP_ERROR_CHECK(ledc_channel_config(&ledc_channel)); + } + else + { + ESP_ERROR_CHECK(ledc_stop(LEDC_MODE, configuration->channel, 0)); + } +} + +static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct esp_pwm *_pwm = rt_container_of(device, struct esp_pwm, pwm_device); + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + switch (cmd) + { + case PWM_CMD_ENABLE: + pwm_enabled(_pwm, configuration, RT_TRUE); + return RT_EOK; + case PWM_CMD_DISABLE: + pwm_enabled(_pwm, configuration, RT_FALSE); + return RT_EOK; + case PWM_CMD_SET: + return _pwm_set(_pwm, configuration); + case PWM_CMD_GET: + return _pwm_get(_pwm, configuration); + default: + return -RT_EINVAL; + } +} + +static struct rt_pwm_ops _pwm_ops = { + _pwm_control +}; + +int rt_hw_pwm_init(void) +{ + int result = RT_EOK; + + for (int i = 0; i < sizeof(esp_pwm_obj) / sizeof(esp_pwm_obj[0]); i++) + { + esp_pwm_obj[i].timer_num = i; + result = rt_device_pwm_register(&esp_pwm_obj[i].pwm_device, esp_pwm_obj[i].name, &_pwm_ops, 0); + if (result != RT_EOK) + { + LOG_E("%s register fail.", esp_pwm_obj[i].name); + } + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_PWM */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.h new file mode 100644 index 000000000000..ad0652474bd5 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_pwm.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-20 ChuShicheng first version + */ + +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include + +int rt_hw_pwm_init(void); + +#endif /* __DRV_PWM_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.c new file mode 100644 index 000000000000..fcb38633e8e0 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 wumingzi first implementation + * 2024-10-08 wumingzi add custom configuration and support muti spi obj + */ + +#include +#include +#include + +#include "rtdef.h" +#include "rttypes.h" +#include "sdkconfig.h" + + +#include "hal/spi_hal.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/hal/include/hal/spi_types.h*/ +#include "driver/gpio.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/gpio.h*/ +#include "driver/spi_master.h" +/* ESP-IDF v6.1's driver/spi_master.h no longer pulls in the FreeRTOS headers, + * but portMAX_DELAY below comes from FreeRTOS's portmacro.h. */ +#include + +#include "drv_spi.h" +#include "drivers/dev_spi.h" + +#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI2 +#define LOG_TAG "drv.spi" +#include + +static struct rt_spi_bus spi_bus2; + +static spi_device_handle_t spi; +static spi_bus_config_t buscfg; + +/* + * Width of one data unit of the transaction, in bits. spi_transaction_t counts + * length/rxlength in bits, so spixfer() needs this to size the transfer and to + * know how wide the received units it copies out are. + * Only 8-bit words are supported; spi_configure() rejects anything else. + */ +static rt_uint32_t spi_bits_per_word = 8; + +/* + * Receive staging array. driver/spi_master.h says of spi_transaction_t.rx_buffer + * "Written by 4 bytes-unit if DMA is used", so the received bytes are taken into + * an aligned array of our own and only message->length of them are handed to the + * caller -- whose buffer may be any size and alignment. Sized for + * buscfg.max_transfer_sz. Where those bytes come from is chip specific and told + * where the chip decides it: see spi_configure(). + */ +#define RT_ESP_SPI_MAX_RX_BYTES 4092 +static rt_uint32_t spi_rx_units[(RT_ESP_SPI_MAX_RX_BYTES + 3) / 4] __attribute__((aligned(4))); + +/* + * Largest number of bytes one spi_transaction_t may carry. With DMA enabled + * this is buscfg.max_transfer_sz; with SPI_DMA_DISABLED (C6) spi_common.c sets + * bus_attr->max_transfer_sz to SOC_SPI_MAXIMUM_BUFFER_SIZE (64 on C6) and + * spi_master.c rejects a longer transaction with ESP_ERR_INVALID_ARG, so + * spixfer() splits longer messages into chunks and keeps CS asserted between + * them. + */ +#ifdef SOC_ESP32_C6 +#define RT_ESP_SPI_MAX_CHUNK_BYTES SOC_SPI_MAXIMUM_BUFFER_SIZE +#else +#define RT_ESP_SPI_MAX_CHUNK_BYTES RT_ESP_SPI_MAX_RX_BYTES +#endif + +static struct esp32_spi spi_bus_obj[] = { +#ifdef BSP_USING_SPI2 + { + .bus_name = "spi2", + .spi_bus = &spi_bus2, + .esp32_spi_bus_cfg = &buscfg, + }, +#endif /* BSP_USING_SPI2 */ +}; + +/* private rt-thread spi ops function */ +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message); + +static struct rt_spi_ops esp32_spi_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; + +static rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + if (configuration == NULL) + { + return -RT_EINVAL; + } + + /* Validate the word width before touching the hardware. An unsupported + * width must not leave an initialized SPI bus behind: a caller that asks + * for 16 bits and then retries with 8 would otherwise hit + * spi_bus_initialize()'s "bus already initialized" abort. */ + if (configuration->data_width != 8) + { + LOG_E("data width %u is not supported\n", (rt_uint32_t)configuration->data_width); + return -RT_ENOSYS; + } + /* One RT-Thread byte is 8 bits of transaction: this is what length and + * rxlength are counted in. */ + spi_bits_per_word = 8; + + static spi_bus_config_t buscfg = { + .miso_io_num = SPI2_IOMUX_PIN_NUM_MISO, /*MISO*/ + .mosi_io_num = SPI2_IOMUX_PIN_NUM_MOSI, /*MOSI*/ + .sclk_io_num = SPI2_IOMUX_PIN_NUM_CLK, /*CLK*/ + .quadwp_io_num = -1, /*不使用*/ + .quadhd_io_num = -1, /*不使用*/ + .max_transfer_sz = 4092 /*最大传送数据长度*/ + }; + + esp_err_t err; + +#ifdef SOC_ESP32_C6 + /* SPI_DMA_DISABLED: this transfer does not go through GDMA, even though GDMA + is in the image -- BSP_USING_SPI makes idf_port/SConscript compile this + BSP's own src/gdma.c, because spi_common.c's SOC_GDMA_SUPPORTED section + calls it. The received bytes are instead read out by spi_ll_read_buffer() + (hal/esp32c6/include/hal/spi_ll.h:425), which memcpys the low byte of each + 32-bit data_buf word to the start of the buffer -- its length is + (len + 7) / 8, which is 1 for an 8-bit word -- and that is what fills the + staging array above. */ + err = spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_DISABLED); +#else + err = spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO); +#endif /* SOC_ESP32_C6 */ + ESP_ERROR_CHECK(err); + + static spi_device_interface_config_t devcfg; + + LOG_W("configuration->max_hz = %d \n", configuration->max_hz); + if (configuration->max_hz >= SPI_MASTER_FREQ_80M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_80M; /*/< 80MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_40M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_40M; /*/< 40MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_26M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_26M; /*/< 26.67MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_20M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_20M; /*/< 20MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_16M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_16M; /*/< 16MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_13M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_13M; /*/< 13.33MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_11M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_11M; /*/< 11.43MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_10M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_10M; /*/< 10MHz*/ + } + else if (configuration->max_hz >= SPI_MASTER_FREQ_9M) + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_9M; /*/< 8.89MHz*/ + } + else + { + devcfg.clock_speed_hz = SPI_MASTER_FREQ_8M; + } + + switch (configuration->mode) + { + case RT_SPI_MODE_0: /*!< CPOL = 0, CPHA = 0 */ + devcfg.mode = 0; + break; + case RT_SPI_MODE_1: /*!< CPOL = 0, CPHA = 1 */ + devcfg.mode = 1; + break; + case RT_SPI_MODE_2: /*!< CPOL = 1, CPHA = 0 */ + devcfg.mode = 2; + break; + case RT_SPI_MODE_3: /*!< CPOL = 1, CPHA = 1 */ + devcfg.mode = 3; + break; + default: + devcfg.mode = 0; + break; + } + + /* todo: support changing cs_pin,queue_size or specifing spi_device_interface_config_t and + * spi_transaction_t by resever data.Meanwhile finish the initialization of interrupt + * callback function and dma. + */ + + devcfg.spics_io_num = SPI2_IOMUX_PIN_NUM_CS; + devcfg.queue_size = 7; + + err = spi_bus_add_device(SPI2_HOST, &devcfg, &spi); + ESP_ERROR_CHECK(err); + + /* Although there is only one spi bus object, it will be a template for other bsps of ESP32 series */ + for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++) + { + spi_bus_obj[i].bus_name = "spi2"; + spi_bus_obj[i].spi_bus = &spi_bus2; + spi_bus_obj[i].esp32_spi_bus_cfg = &buscfg; + } + + return RT_EOK; +}; + +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + if (message->recv_buf != RT_NULL && message->length > sizeof(spi_rx_units)) + { + LOG_E("rx length %u is larger than %u\n", + (rt_uint32_t)message->length, (rt_uint32_t)RT_ESP_SPI_MAX_RX_BYTES); + return -RT_EINVAL; + } + + rt_size_t total = message->length; + rt_size_t done = 0; + static spi_transaction_t trans; + + spi_device_acquire_bus(spi, portMAX_DELAY); + + while (done < total) + { + rt_size_t chunk = total - done; + if (chunk > RT_ESP_SPI_MAX_CHUNK_BYTES) + { + chunk = RT_ESP_SPI_MAX_CHUNK_BYTES; + } + + /* Zeroed per chunk: this transaction is reused, and cmd/addr/flags/user + left over from the previous one would be sent out again. */ + rt_memset(&trans, 0, sizeof(trans)); + + trans.length = chunk * spi_bits_per_word; + if (message->send_buf != RT_NULL) + { + trans.tx_buffer = (const rt_uint8_t *)message->send_buf + done; + } + + if (message->recv_buf != RT_NULL) + { + /* The driver writes the received units into this 4-byte aligned + array, not into the caller's buffer. */ + trans.rx_buffer = spi_rx_units; + trans.rxlength = trans.length; + } + + /* Hold CS across chunk boundaries; the last chunk lets the driver + release it. The bus is acquired above, which is what allows the + KEEP_ACTIVE flag in a polling transaction. */ + if (done + chunk < total) + { + trans.flags |= SPI_TRANS_CS_KEEP_ACTIVE; + } + + esp_err_t err = spi_device_polling_transmit(spi, &trans); + if (err != ESP_OK) + { + LOG_E("spi transfer failed at offset %u: %d\n", + (rt_uint32_t)done, err); + spi_device_release_bus(spi); + return -RT_EIO; + } + + if (message->recv_buf != RT_NULL) + { + /* Verbatim: the aligned array holds the received bytes in the order + they came off the bus, and only the count the caller asked for is + copied. */ + rt_memcpy((rt_uint8_t *)message->recv_buf + done, spi_rx_units, chunk); + } + + done += chunk; + } + + spi_device_release_bus(spi); + + return total; +}; + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + rt_device_t busp = RT_NULL; + struct rt_spi_device *spi_device; + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + +int rt_hw_spi_init(void) +{ + int result = 0; + + for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++) + { + spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i]; + result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &esp32_spi_ops); + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_bus_obj[i].bus_name); + } + + return result; +} + +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4*/ +#endif /* RT_USING_SPI */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.h new file mode 100644 index 000000000000..f25ba9a49e10 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_spi.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-08 wumingzi first implementation + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include +#include +#include "driver/spi_common.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/spi_common.h*/ +#ifdef __cplusplus +extern "C" { +#endif + +/* esp32 spi dirver class */ +struct esp32_spi +{ + char *bus_name; + struct rt_spi_bus *spi_bus; + spi_bus_config_t *esp32_spi_bus_cfg; +}; + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.c new file mode 100644 index 000000000000..b2db247181d6 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-15 BetMul first version + */ + +#include "drv_timer.h" + +#include +#include +#include "driver/gptimer.h" +#include "sdkconfig.h" + +#ifdef RT_USING_CLOCK_TIME + +/** + * handle interrupt for clock_timer. + */ +static bool mcu_clock_timer_intr_handler(gptimer_handle_t gptimer, const gptimer_alarm_event_data_t *edata, void *user_ctx) +{ + rt_interrupt_enter(); + + rt_clock_timer_t *clock_timer = (rt_clock_timer_t *)user_ctx; + rt_clock_timer_isr(clock_timer); + + rt_interrupt_leave(); + + return 0; +} + +/** + * init the clock_timer +*/ +static void mcu_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) +{ + gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; + + // let the gptimer into enable status + ESP_ERROR_CHECK(gptimer_enable(gptimer)); +} + +/** + * start the clock_timer, change status into running +*/ +static rt_err_t mcu_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) +{ + gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; + gptimer_alarm_config_t alarm_config = { + .alarm_count = cnt, + }; + if (mode == CLOCK_TIMER_MODE_ONESHOT) + { + } + else + { + alarm_config.reload_count = 0; + alarm_config.flags.auto_reload_on_alarm = true; + } + ESP_ERROR_CHECK(gptimer_set_alarm_action(gptimer, &alarm_config)); + ESP_ERROR_CHECK(gptimer_start(gptimer)); + + return RT_EOK; +} + +/** + * stop the clock_timer, change the status from running into enable +*/ +static void mcu_clock_timer_stop(rt_clock_timer_t *timer) +{ + gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; + + ESP_ERROR_CHECK(gptimer_stop(gptimer)); +} + +/** + * get count +*/ +static rt_uint32_t mcu_clock_timer_count_get(rt_clock_timer_t *timer) +{ + gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; + // get count number + uint64_t value; + ESP_ERROR_CHECK(gptimer_get_raw_count(gptimer, &value)); + return (rt_uint32_t)value; +} + +/** + * control the clock_timer +*/ +static rt_err_t mcu_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t err = RT_EOK; + + switch (cmd) + { + case CLOCK_TIMER_CTRL_FREQ_SET: + err = -RT_ERROR; + break; + + case CLOCK_TIMER_CTRL_INFO_GET: + err = -RT_ERROR; + break; + + case CLOCK_TIMER_CTRL_MODE_SET: + timer->mode = *(rt_uint32_t *)args; + break; + + case CLOCK_TIMER_CTRL_STOP: + mcu_clock_timer_stop(timer); + break; + } + + return err; +} + +static struct rt_clock_timer_device _clock_timer; +static const struct rt_clock_timer_ops _clock_timer_ops = { + .init = mcu_clock_timer_init, + .start = mcu_clock_timer_start, + .stop = mcu_clock_timer_stop, + .count_get = mcu_clock_timer_count_get, + .control = mcu_clock_timer_control +}; + +static const struct rt_clock_timer_info _clock_timer_info = { + // TODO:what is the true max and min? + .maxfreq = 1000000UL, + .minfreq = 1000000UL, + .maxcnt = 0xFFFF, + .cntmode = CLOCK_TIMER_MODE_ONESHOT +}; + +int rt_hw_clock_timer_init(void) +{ + char *name = "timer0"; + + gptimer_handle_t gptimer = NULL; + gptimer_config_t timer_config = { + .clk_src = GPTIMER_CLK_SRC_DEFAULT, + .direction = GPTIMER_COUNT_UP, + .resolution_hz = 1 * 1000 * 1000, + }; + + gptimer_event_callbacks_t cbs = { + .on_alarm = mcu_clock_timer_intr_handler, + }; + + ESP_ERROR_CHECK(gptimer_new_timer(&timer_config, &gptimer)); + ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimer, &cbs, &_clock_timer)); + + _clock_timer.info = &_clock_timer_info; + _clock_timer.ops = &_clock_timer_ops; + + return rt_clock_timer_register(&_clock_timer, name, (void *)gptimer); +} + +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.h new file mode 100644 index 000000000000..87a1ee495c72 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_timer.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-15 BetMul first version + */ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ + +#include + +#ifdef RT_USING_CLOCK_TIME +int rt_hw_clock_timer_init(void); +#endif + + +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.c new file mode 100644 index 000000000000..4278be77345d --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-04 tangzz98 first version + * + */ + +#include +#include +#include "driver/uart.h" +#include "hal/uart_hal.h" +#include "hal/uart_periph.h" +#include "sdkconfig.h" +#ifdef RT_USING_SERIAL_V1 + +#ifdef CONFIG_UART_ISR_IN_IRAM +#define UART_ISR_ATTR IRAM_ATTR +#else +#define UART_ISR_ATTR +#endif + +uart_hal_context_t hal[] = { + { + .dev = &UART0, + }, + { + .dev = &UART1, + }, +}; + +static struct rt_serial_device _serial; + +static void mcu_uart_rx_intr_handler(void *param) +{ + uint32_t uart_intr_status; + struct rt_serial_device *serial; + uart_port_t port; + rt_interrupt_enter(); + serial = (struct rt_serial_device *)param; + port = (uart_port_t)serial->parent.user_data; + uart_intr_status = uart_hal_get_intsts_mask(&hal[port]); + if (uart_intr_status != 0) + { + if (uart_intr_status & UART_INTR_RXFIFO_FULL) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + uart_hal_clr_intsts_mask(&hal[port], uart_intr_status); + } + rt_interrupt_leave(); +} + +static rt_err_t mcu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + return RT_EOK; +} + +static rt_err_t mcu_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + return RT_EOK; +} + +static int mcu_uart_putc(struct rt_serial_device *serial, char c) +{ + uart_port_t port = (uart_port_t)serial->parent.user_data; + uint32_t write_size = 0; + do + { + uart_hal_write_txfifo(&hal[port], (const uint8_t *)&c, 1, &write_size); + } while (write_size == 0); + + return 1; +} + +static int mcu_uart_getc(struct rt_serial_device *serial) +{ + uart_port_t port = (uart_port_t)serial->parent.user_data; + uint8_t c; + int len = uart_hal_get_rxfifo_len(&hal[port]); + if (len == 0) + { + return -1; + } + else + { + len = 1; + uart_hal_read_rxfifo(&hal[port], &c, &len); + return (int)c; + } +} + +static const struct rt_uart_ops _uart_ops = { + mcu_uart_configure, + mcu_uart_control, + mcu_uart_putc, + mcu_uart_getc, + RT_NULL, +}; + +int rt_hw_uart_init(void) +{ + uart_intr_config_t uart_intr = { + .intr_enable_mask = UART_INTR_RXFIFO_FULL, + .rxfifo_full_thresh = 1, + }; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + uart_config_t uart_config = { + .baud_rate = BAUD_RATE_115200, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, +#ifdef SOC_ESP32_C6 + .source_clk = UART_SCLK_DEFAULT, +#else + .source_clk = UART_SCLK_APB, +#endif + }; + int intr_alloc_flags = 0; + +#if CONFIG_UART_ISR_IN_IRAM + intr_alloc_flags = ESP_INTR_FLAG_IRAM; +#endif + + ESP_ERROR_CHECK(uart_param_config(RT_BSP_UART_PORT, &uart_config)); + ESP_ERROR_CHECK(uart_set_pin(RT_BSP_UART_PORT, RT_BSP_UART_TX_PIN, RT_BSP_UART_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE)); + ESP_ERROR_CHECK(esp_intr_alloc(uart_periph_signal[RT_BSP_UART_PORT].irq, intr_alloc_flags, mcu_uart_rx_intr_handler, (void *)&_serial, NULL)); + ESP_ERROR_CHECK(uart_intr_config(RT_BSP_UART_PORT, &uart_intr)); + _serial.ops = &_uart_ops; + _serial.config = config; + + return rt_hw_serial_register(&_serial, "uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, (void *)RT_BSP_UART_PORT); +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL_V1 */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.h new file mode 100644 index 000000000000..f47a29b116a3 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_uart.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-04 tangzz98 first version + * + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include + +#ifdef RT_USING_SERIAL_V1 +int rt_hw_uart_init(void); +#endif + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.c b/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.c new file mode 100644 index 000000000000..22b9f4d297f6 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.c @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2019 Winner Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-25 WCX1024979076 1st version + */ + +#include +#include +#include + +#ifdef RT_USING_WIFI +#include "drv_wifi.h" +#include "esp_system.h" +#include "esp_wifi.h" +#include "esp_event.h" +#include "esp_log.h" +#include "esp_timer.h" +#include "nvs_flash.h" +#include "esp_private/wifi.h" + +#define DBG_LEVEL DBG_LOG +#define LOG_TAG "DRV.WIFI" +#include + +#define MAX_ADDR_LEN (6) + +struct drv_wifi +{ + struct rt_wlan_device *wlan; + wifi_interface_t wifi_if; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; +}; + +static const struct rt_wlan_dev_ops ops; +static struct drv_wifi wifi_sta; +static struct drv_wifi wifi_ap; + +#define EXAMPLE_ESP_MAXIMUM_RETRY 5 +#define DEFAULT_SCAN_LIST_SIZE 3 +static int s_retry_num = 0; + +wifi_ap_record_t ap_info[DEFAULT_SCAN_LIST_SIZE]; + +static rt_err_t drv_wlan_scan_stop(struct rt_wlan_device *wlan); + +static void wifi_event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data) +{ + if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_AP_START) + { + rt_wlan_dev_indicate_event_handle(wifi_ap.wlan, RT_WLAN_DEV_EVT_AP_START, RT_NULL); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_AP_STOP) + { + rt_wlan_dev_indicate_event_handle(wifi_ap.wlan, RT_WLAN_DEV_EVT_AP_STOP, RT_NULL); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_AP_STACONNECTED) + { + wifi_event_ap_staconnected_t *event = (wifi_event_ap_staconnected_t *)event_data; + rt_wlan_dev_indicate_event_handle(wifi_ap.wlan, RT_WLAN_DEV_EVT_AP_ASSOCIATED, RT_NULL); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_AP_STADISCONNECTED) + { + wifi_event_ap_stadisconnected_t *event = (wifi_event_ap_stadisconnected_t *)event_data; + rt_wlan_dev_indicate_event_handle(wifi_ap.wlan, RT_WLAN_DEV_EVT_AP_DISASSOCIATED, RT_NULL); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_START) + { + esp_wifi_connect(); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_CONNECTED) + { + rt_wlan_dev_indicate_event_handle(wifi_sta.wlan, RT_WLAN_DEV_EVT_CONNECT, RT_NULL); + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_DISCONNECTED) + { + if (s_retry_num < EXAMPLE_ESP_MAXIMUM_RETRY) + { + esp_wifi_connect(); + s_retry_num++; + } + else + { + rt_wlan_dev_indicate_event_handle(wifi_sta.wlan, RT_WLAN_DEV_EVT_CONNECT_FAIL, RT_NULL); + } + } + else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_SCAN_DONE) + { + drv_wlan_scan_stop(RT_NULL); + } +} + +static esp_err_t wifi_sta_receive(void *buffer, uint16_t len, void *eb) +{ + rt_wlan_dev_report_data(wifi_sta.wlan, buffer, len); + return RT_EOK; +} + +static esp_err_t wifi_ap_receive(void *buffer, uint16_t len, void *eb) +{ + rt_wlan_dev_report_data(wifi_ap.wlan, buffer, len); + return RT_EOK; +} + +void wifi_init_sta(void) +{ +} + +void wifi_init_softap(void) +{ +} + +/* Initialize Wi-Fi as sta and set scan method */ +static rt_err_t drv_wlan_scan(struct rt_wlan_device *wlan, struct rt_scan_info *scan_info) +{ + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); + ESP_ERROR_CHECK(esp_wifi_start()); + esp_wifi_scan_start(NULL, false); +} + +static rt_err_t drv_wlan_init(struct rt_wlan_device *wlan) +{ + // 初始化时钟以及事件处理 + esp_timer_init(); + esp_event_loop_create_default(); + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_wifi_init(&cfg)); + + esp_event_handler_instance_t instance_any_id; + ESP_ERROR_CHECK(esp_event_handler_instance_register(WIFI_EVENT, + ESP_EVENT_ANY_ID, + &wifi_event_handler, + NULL, + &instance_any_id)); + + // 注册收到内容回调 + ESP_ERROR_CHECK(esp_wifi_internal_reg_rxcb(WIFI_IF_STA, wifi_sta_receive)); + ESP_ERROR_CHECK(esp_wifi_internal_reg_rxcb(WIFI_IF_AP, wifi_ap_receive)); + + return RT_EOK; +} + +static rt_err_t drv_wlan_mode(struct rt_wlan_device *wlan, rt_wlan_mode_t mode) +{ + if (mode == RT_WLAN_STATION) + { + wifi_init_sta(); + } + else + { + wifi_init_softap(); + } + return RT_EOK; +} + + +static rt_err_t drv_wlan_join(struct rt_wlan_device *wlan, struct rt_sta_info *sta_info) +{ + wifi_config_t wifi_config = { + .sta = { + .ssid = "", + .password = "", + /* Authmode threshold resets to WPA2 as default if password matches WPA2 standards (pasword len => 8). + * If you want to connect the device to deprecated WEP/WPA networks, Please set the threshold value + * to WIFI_AUTH_WEP/WIFI_AUTH_WPA_PSK and set the password with length and format matching to + * WIFI_AUTH_WEP/WIFI_AUTH_WPA_PSK standards. + */ + .threshold.authmode = WIFI_AUTH_WPA_WPA2_PSK, + .sae_pwe_h2e = WPA3_SAE_PWE_BOTH, + }, + }; + rt_memcpy(wifi_config.sta.ssid, sta_info->ssid.val, sta_info->ssid.len); + rt_memcpy(wifi_config.sta.password, sta_info->key.val, sta_info->key.len); + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + return RT_EOK; +} + +static rt_err_t drv_wlan_softap(struct rt_wlan_device *wlan, struct rt_ap_info *ap_info) +{ + wifi_config_t wifi_config = { + .ap = { + .ssid = "", + .ssid_len = 0, + .channel = 3, + .password = "", + .max_connection = 3, + .authmode = WIFI_AUTH_WPA_WPA2_PSK, + .pmf_cfg = { + .required = false, + }, + }, + }; + rt_memcpy(wifi_config.ap.ssid, ap_info->ssid.val, ap_info->ssid.len); + rt_memcpy(wifi_config.ap.password, ap_info->key.val, ap_info->key.len); + wifi_config.ap.ssid_len = ap_info->ssid.len; + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_AP)); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_AP, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + + drv_wlan_scan_stop(RT_NULL); + return RT_EOK; +} + +static rt_err_t drv_wlan_disconnect(struct rt_wlan_device *wlan) +{ + ESP_ERROR_CHECK(esp_wifi_disconnect()); + return RT_EOK; +} + +static rt_err_t drv_wlan_ap_stop(struct rt_wlan_device *wlan) +{ + return RT_EOK; +} + +static rt_err_t drv_wlan_ap_deauth(struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + return RT_EOK; +} + +static rt_err_t drv_wlan_scan_stop(struct rt_wlan_device *wlan) +{ + struct rt_wlan_info wlan_info; + struct rt_wlan_buff buff; + uint16_t number = DEFAULT_SCAN_LIST_SIZE; + uint16_t ap_count = 0; + + memset(ap_info, 0, sizeof(ap_info)); + + ESP_ERROR_CHECK(esp_wifi_scan_get_ap_records(&number, ap_info)); + ESP_ERROR_CHECK(esp_wifi_scan_get_ap_num(&ap_count)); + for (int i = 0; (i < DEFAULT_SCAN_LIST_SIZE) && (i < ap_count); i++) + { + rt_memset(&wlan_info, 0, sizeof(wlan_info)); + rt_memcpy(&wlan_info.bssid[0], ap_info[i].bssid, 6); + rt_memcpy(wlan_info.ssid.val, ap_info[i].ssid, strlen(ap_info[i].ssid)); + + wlan_info.ssid.len = strlen(ap_info[i].ssid); + wlan_info.hidden = 0; + wlan_info.channel = (rt_int16_t)ap_info[i].primary; + wlan_info.rssi = -(char)(0x100 - ap_info[i].rssi); + wlan_info.band = RT_802_11_BAND_2_4GHZ; + wlan_info.security = SECURITY_UNKNOWN; + + buff.data = &wlan_info; + buff.len = sizeof(wlan_info); + rt_wlan_dev_indicate_event_handle(wifi_sta.wlan, RT_WLAN_DEV_EVT_SCAN_REPORT, &buff); + } + esp_wifi_scan_stop(); + return RT_EOK; +} + +static int drv_wlan_get_rssi(struct rt_wlan_device *wlan) +{ + return 0; +} + +static rt_err_t drv_wlan_set_powersave(struct rt_wlan_device *wlan, int level) +{ + return RT_EOK; +} + +static int drv_wlan_get_powersave(struct rt_wlan_device *wlan) +{ + return 0; +} + +static rt_err_t drv_wlan_cfg_promisc(struct rt_wlan_device *wlan, rt_bool_t start) +{ + return RT_EOK; +} + +static rt_err_t drv_wlan_cfg_filter(struct rt_wlan_device *wlan, struct rt_wlan_filter *filter) +{ + return -RT_EINVAL;/* not support */ +} + +static rt_err_t drv_wlan_set_channel(struct rt_wlan_device *wlan, int channel) +{ + return RT_EOK; +} + +static int drv_wlan_get_channel(struct rt_wlan_device *wlan) +{ + return 0; +} + +static rt_err_t drv_wlan_set_country(struct rt_wlan_device *wlan, rt_country_code_t country_code) +{ + return RT_EOK; +} + +static rt_country_code_t drv_wlan_get_country(struct rt_wlan_device *wlan) +{ + return 0; //RT_EOK; +} + +static rt_err_t drv_wlan_set_mac(struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + return RT_EOK; +} + +static rt_err_t drv_wlan_get_mac(struct rt_wlan_device *wlan, rt_uint8_t mac[]) +{ + return RT_EOK; +} + +static int drv_wlan_recv(struct rt_wlan_device *wlan, void *buff, int len) +{ + return RT_EOK; +} + +static int drv_wlan_send(struct rt_wlan_device *wlan, void *buff, int len) +{ + struct drv_wifi *wifi = wlan->user_data; + esp_wifi_internal_tx(wifi->wifi_if, buff, len); + return RT_EOK; +} + +static const struct rt_wlan_dev_ops ops = { + .wlan_init = drv_wlan_init, + .wlan_mode = drv_wlan_mode, + .wlan_scan = drv_wlan_scan, + .wlan_join = drv_wlan_join, + .wlan_softap = drv_wlan_softap, + .wlan_disconnect = drv_wlan_disconnect, + .wlan_ap_stop = drv_wlan_ap_stop, + .wlan_ap_deauth = drv_wlan_ap_deauth, + .wlan_scan_stop = drv_wlan_scan_stop, + .wlan_get_rssi = drv_wlan_get_rssi, + .wlan_set_powersave = drv_wlan_set_powersave, + .wlan_get_powersave = drv_wlan_get_powersave, + .wlan_cfg_promisc = drv_wlan_cfg_promisc, + .wlan_cfg_filter = drv_wlan_cfg_filter, + .wlan_set_channel = drv_wlan_set_channel, + .wlan_get_channel = drv_wlan_get_channel, + .wlan_set_country = drv_wlan_set_country, + .wlan_get_country = drv_wlan_get_country, + .wlan_set_mac = drv_wlan_set_mac, + .wlan_get_mac = drv_wlan_get_mac, + .wlan_recv = drv_wlan_recv, + .wlan_send = drv_wlan_send, +}; + +int rt_hw_wifi_init(void) +{ + // 初始化nvs_flash + esp_err_t esp_ret = nvs_flash_init(); + + if (esp_ret == ESP_ERR_NVS_NO_FREE_PAGES || esp_ret == ESP_ERR_NVS_NEW_VERSION_FOUND) + { + ESP_ERROR_CHECK(nvs_flash_erase()); + esp_ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(esp_ret); + + // 向系统注册 + static struct rt_wlan_device wlan; + static struct rt_wlan_device wlan2; + + rt_memset(&wifi_sta, 0, sizeof(wifi_sta)); + wifi_sta.wifi_if = WIFI_IF_STA; + rt_err_t ret = rt_wlan_dev_register(&wlan, RT_WLAN_DEVICE_STA_NAME, &ops, 0, &wifi_sta); + wifi_sta.wlan = &wlan; + + rt_memset(&wifi_ap, 0, sizeof(wifi_ap)); + wifi_ap.wifi_if = WIFI_IF_AP; + ret |= rt_wlan_dev_register(&wlan2, RT_WLAN_DEVICE_AP_NAME, &ops, 0, &wifi_ap); + wifi_ap.wlan = &wlan2; + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_wifi_init); + +#endif /* RT_USING_WIFI */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.h b/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.h new file mode 100644 index 000000000000..42b6e0b55aff --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/drv_wifi.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019 Winner Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-25 WCX1024979076 1st version + */ + +#ifndef __DRV_WIFI_H__ +#define __DRV_WIFI_H__ + +#ifdef RT_USING_WIFI +int rt_hw_wifi_init(void); +#endif /* RT_USING_WIFI */ + +#endif /* __DRV_WIFI_H__ */ diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig.h b/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig.h new file mode 100644 index 000000000000..a64bcd994ac1 --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig.h @@ -0,0 +1,841 @@ +/* + * Automatically generated file. DO NOT EDIT. + * Espressif IoT Development Framework (ESP-IDF) Configuration Header + */ +#include "rtconfig.h" +#pragma once +/* + * ESP-IDF v6.1 moved the newlib compatibility shims into esp_libc. They are + * only enabled when CONFIG_LIBC_NEWLIB is set, otherwise esp_libc declares an + * empty `struct _reent` and the toolchain's fails to compile. + * The scons build links against the toolchain's newlib, so enable it. + */ +#define CONFIG_LIBC_NEWLIB 1 +/* new in ESP-IDF v6.1 (components/esp_libc/Kconfig), default 200 */ +#define CONFIG_LIBC_ASSERT_BUFFER_SIZE 200 +/* ESP-IDF v6.1 split esp_log into V1/V2 variants (components/log/Kconfig). */ +#define CONFIG_LOG_VERSION 1 +#ifdef SOC_ESP32_C6 +#include "sdkconfig_c6.h" +#else +#define CONFIG_SOC_ADC_SUPPORTED 1 +#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1 +#define CONFIG_SOC_GDMA_SUPPORTED 1 +#define CONFIG_SOC_TWAI_SUPPORTED 1 +#define CONFIG_SOC_BT_SUPPORTED 1 +#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1 +#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1 +#define CONFIG_SOC_XT_WDT_SUPPORTED 1 +#define CONFIG_SOC_WIFI_SUPPORTED 1 +#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1 +#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG 1 +#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1 +#define CONFIG_SOC_RTC_MEM_SUPPORTED 1 +#define CONFIG_SOC_I2S_SUPPORTED 1 +#define CONFIG_SOC_RMT_SUPPORTED 1 +#define CONFIG_SOC_SDM_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_SUPPORTED 1 +#define CONFIG_SOC_SUPPORT_COEXISTENCE 1 +#define CONFIG_SOC_AES_SUPPORTED 1 +#define CONFIG_SOC_MPI_SUPPORTED 1 +#define CONFIG_SOC_SHA_SUPPORTED 1 +#define CONFIG_SOC_HMAC_SUPPORTED 1 +#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1 +#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1 +#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1 +#define CONFIG_SOC_MEMPROT_SUPPORTED 1 +#define CONFIG_SOC_XTAL_SUPPORT_40M 1 +#define CONFIG_SOC_AES_SUPPORT_DMA 1 +#define CONFIG_SOC_AES_GDMA 1 +#define CONFIG_SOC_AES_SUPPORT_AES_128 1 +#define CONFIG_SOC_AES_SUPPORT_AES_256 1 +#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1 +#define CONFIG_SOC_ADC_FILTER_SUPPORTED 1 +#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1 +#define CONFIG_SOC_ADC_DMA_SUPPORTED 1 +#define CONFIG_SOC_ADC_PERIPH_NUM 2 +#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 5 +#define CONFIG_SOC_ADC_ATTEN_NUM 4 +#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 1 +#define CONFIG_SOC_ADC_PATT_LEN_MAX 8 +#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12 +#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12 +#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4 +#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4 +#define CONFIG_SOC_ADC_DIGI_FILTER_NUM 2 +#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2 +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12 +#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12 +#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1 +#define CONFIG_SOC_APB_BACKUP_DMA 1 +#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1 +#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1 +#define CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 +#define CONFIG_SOC_CPU_CORES_NUM 1 +#define CONFIG_SOC_CPU_INTR_NUM 32 +#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 8 +#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 8 +#define CONFIG_SOC_CPU_WATCHPOINT_SIZE 0x80000000 +#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 3072 +#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16 +#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100 +#define CONFIG_SOC_GDMA_GROUPS 1 +#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP 3 +#define CONFIG_SOC_GDMA_TX_RX_SHARE_INTERRUPT 1 +#define CONFIG_SOC_GPIO_PORT 1 +#define CONFIG_SOC_GPIO_PIN_COUNT 22 +#define CONFIG_SOC_GPIO_SUPPORTS_RTC_INDEPENDENT 1 +#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1 +#define CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1 +#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK 0 +#define CONFIG_SOC_GPIO_SUPPORT_SLP_SWITCH 1 +#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM 8 +#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM 8 +#define CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE 1 +#define CONFIG_SOC_I2C_NUM 1 +#define CONFIG_SOC_I2C_FIFO_LEN 32 +#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1 +#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS 1 +#define CONFIG_SOC_I2C_SUPPORT_XTAL 1 +#define CONFIG_SOC_I2C_SUPPORT_RTC 1 +#define CONFIG_SOC_I2S_NUM 1 +#define CONFIG_SOC_I2S_HW_VERSION_2 1 +#define CONFIG_SOC_I2S_SUPPORTS_PCM 1 +#define CONFIG_SOC_I2S_SUPPORTS_PDM 1 +#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1 +#define CONFIG_SOC_I2S_SUPPORTS_PDM_CODEC 1 +#define CONFIG_SOC_I2S_SUPPORTS_TDM 1 +#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1 +#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1 +#define CONFIG_SOC_LEDC_CHANNEL_NUM 6 +#define CONFIG_SOC_LEDC_TIMER_BIT_WIDE_NUM 14 +#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1 +#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000 +#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8 +#define CONFIG_SOC_RMT_GROUPS 1 +#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 2 +#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 2 +#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4 +#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48 +#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1 +#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1 +#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 +#define CONFIG_SOC_RMT_SUPPORT_XTAL 1 +#define CONFIG_SOC_RMT_SUPPORT_APB 1 +#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1 +#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128 +#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 108 +#define CONFIG_SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 1 +#define CONFIG_SOC_RTCIO_PIN_COUNT 0 +#define CONFIG_SOC_RSA_MAX_BIT_LEN 3072 +#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968 +#define CONFIG_SOC_SHA_SUPPORT_DMA 1 +#define CONFIG_SOC_SHA_SUPPORT_RESUME 1 +#define CONFIG_SOC_SHA_GDMA 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA1 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA224 1 +#define CONFIG_SOC_SHA_SUPPORT_SHA256 1 +#define CONFIG_SOC_SDM_GROUPS 1 +#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 4 +#define CONFIG_SOC_SPI_PERIPH_NUM 2 +#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1 +#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1 +#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 +#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1 +#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS 1 +#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2 +#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3 +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32 +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20 +#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1 +#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1 +#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 +#define CONFIG_SOC_TIMER_GROUPS 2 +#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP 1 +#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54 +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL 1 +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_APB 1 +#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS 2 +#define CONFIG_SOC_TWAI_BRP_MIN 2 +#define CONFIG_SOC_TWAI_BRP_MAX 16384 +#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1 +#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 +#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 +#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 32 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 512 +#define CONFIG_SOC_UART_NUM 2 +#define CONFIG_SOC_UART_FIFO_LEN 128 +#define CONFIG_SOC_UART_BITRATE_MAX 5000000 +#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1 +#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1 +#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1 +#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1 +#define CONFIG_SOC_UART_REQUIRE_CORE_RESET 1 +#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1 +#define CONFIG_SOC_COEX_HW_PTI 1 +#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21 +#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192 +#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12 +#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1 +#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1 +#define CONFIG_SOC_PM_SUPPORT_WIFI_PD 1 +#define CONFIG_SOC_PM_SUPPORT_BT_PD 1 +#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1 +#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL 1 +#define CONFIG_SOC_WIFI_HW_TSF 1 +#define CONFIG_SOC_WIFI_FTM_SUPPORT 1 +#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1 +#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1 +#define CONFIG_SOC_WIFI_CSI_SUPPORT 1 +#define CONFIG_SOC_WIFI_MESH_SUPPORT 1 +#define CONFIG_SOC_BLE_SUPPORTED 1 +#define CONFIG_IDF_CMAKE 1 +#define CONFIG_IDF_TARGET_ARCH_RISCV 1 +#define CONFIG_IDF_TARGET_ARCH "riscv" +#define CONFIG_IDF_TARGET "esp32c3" +#define CONFIG_IDF_TARGET_ESP32C3 1 +#define CONFIG_IDF_RTOS_RTTHREAD 1 +#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005 +#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1 +#define CONFIG_APP_BUILD_GENERATE_BINARIES 1 +#define CONFIG_APP_BUILD_BOOTLOADER 1 +#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 +#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL 3 +/* new in ESP-IDF v6.1 (components/bootloader/Kconfig.projbuild), default 80 */ +#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 80 +/* + * ESP-IDF v6.1 only offers the VDDSDIO boost on chips with a configurable + * VDDSDIO regulator (choice BOOTLOADER_VDDSDIO_BOOST depends on + * SOC_CONFIGURABLE_VDDSDIO_SUPPORTED). The ESP32-C3 has none and its + * soc/rtc.h no longer declares rtc_vddsdio_*_config(). + */ +#if !defined(SOC_ESP32_C3) +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#endif +#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 +#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 +#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 +#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 +#define CONFIG_SECURE_BOOT_V2_PREFERRED 1 +#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1 +#define CONFIG_APP_COMPILE_TIME_DATE 1 +#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 +#define CONFIG_ESP_ROM_HAS_CRC_LE 1 +#define CONFIG_ESP_ROM_HAS_CRC_BE 1 +#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1 +#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1 +#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 3 +#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1 +#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1 +#define CONFIG_ESP_ROM_GET_CLK_FREQ 1 +#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1 +#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1 +#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 +#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_ESPTOOLPY_FLASHMODE_VAL 3 +/* new in ESP-IDF v6.1: eFuse block revision range checked by the 2nd stage + bootloader (components/esp_hw_support/port/esp32c3/Kconfig.hw_support) */ +#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0 +#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199 +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "80m" +#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB" +#define CONFIG_ESPTOOLPY_BEFORE_RESET 1 +#define CONFIG_ESPTOOLPY_BEFORE "default_reset" +#define CONFIG_ESPTOOLPY_AFTER_RESET 1 +#define CONFIG_ESPTOOLPY_AFTER "hard_reset" +#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200 +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_WIFI_SSID "myssid" +#define CONFIG_ESP_WIFI_PASSWORD "mypassword" +#define CONFIG_ESP_MAXIMUM_RETRY 5 +#define CONFIG_ESP_WIFI_AUTH_WPA2_PSK 1 +#endif +#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1 +#define CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2 +#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1 +#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_APPTRACE_DEST_NONE 1 +#define CONFIG_APPTRACE_DEST_UART_NONE 1 +#define CONFIG_APPTRACE_UART_TASK_PRIO 1 +#define CONFIG_APPTRACE_LOCK_ENABLE 1 +#endif +#ifdef BSP_USING_BLE +#define CONFIG_BT_ENABLED 1 +#define CONFIG_BT_NIMBLE_ENABLED 1 +#define CONFIG_BT_CONTROLLER_ENABLED 1 +#define CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL 1 +#define CONFIG_BT_NIMBLE_LOG_LEVEL_INFO 1 +#define CONFIG_BT_NIMBLE_LOG_LEVEL 1 +#define CONFIG_BT_NIMBLE_MAX_CONNECTIONS 3 +#define CONFIG_BT_NIMBLE_MAX_BONDS 3 +#define CONFIG_BT_NIMBLE_MAX_CCCDS 8 +#define CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM 0 +#define CONFIG_BT_NIMBLE_PINNED_TO_CORE 0 +#define CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE 4096 +#define CONFIG_BT_NIMBLE_ROLE_CENTRAL 1 +#define CONFIG_BT_NIMBLE_ROLE_PERIPHERAL 1 +#define CONFIG_BT_NIMBLE_ROLE_BROADCASTER 1 +#define CONFIG_BT_NIMBLE_ROLE_OBSERVER 1 +#define CONFIG_BT_NIMBLE_SECURITY_ENABLE 1 +#define CONFIG_BT_NIMBLE_SM_LEGACY 1 +#define CONFIG_BT_NIMBLE_SM_SC 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_ENCRYPTION 1 +#define CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME "nimble" +#define CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN 31 +#define CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU 256 +#define CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE 0x0 +#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT 12 +#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_SIZE 256 +#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_COUNT 24 +#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_SIZE 320 +#define CONFIG_BT_NIMBLE_ACL_BUF_COUNT 24 +#define CONFIG_BT_NIMBLE_ACL_BUF_SIZE 255 +#define CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE 70 +#define CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT 30 +#define CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT 8 +#define CONFIG_BT_NIMBLE_GATT_MAX_PROCS 4 +#define CONFIG_BT_NIMBLE_RPA_TIMEOUT 900 +#define CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS 1 +#define CONFIG_BT_NIMBLE_HS_STOP_TIMEOUT_MS 2000 +#define CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT 1 +#define CONFIG_BT_NIMBLE_MAX_CONN_REATTEMPT 3 +#define CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_CODED_PHY 1 +#define CONFIG_BT_NIMBLE_MAX_PERIODIC_SYNCS 0 +#define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1 +#define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EFF 0 +#define CONFIG_BT_NIMBLE_WHITELIST_SIZE 12 +#define CONFIG_BT_NIMBLE_USE_ESP_TIMER 1 +#define CONFIG_BT_NIMBLE_LEGACY_VHCI_ENABLE 1 +#define CONFIG_BT_CTRL_MODE_EFF 1 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 +#define CONFIG_BT_CTRL_PINNED_TO_CORE 0 +#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 +#define CONFIG_BT_CTRL_HCI_TL 1 +#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30 +#define CONFIG_BT_CTRL_HW_CCA_VAL 20 +#define CONFIG_BT_CTRL_HW_CCA_EFF 0 +#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1 +#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0 +#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1 +#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0 +#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1 +#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0 +#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P3 1 +#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 9 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20 +#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1 +#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1 +#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0 +#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100 +#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1 +#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0 +#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0 +#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0 +#define CONFIG_BT_CTRL_HCI_TL_EFF 1 +#endif +#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1 +#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1 +#define CONFIG_EFUSE_MAX_BLK_LEN 256 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_TLS_USING_MBEDTLS 1 +#define CONFIG_ESP_TLS_USE_DS_PERIPHERAL 1 +#endif +#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ETH_ENABLED 1 +#define CONFIG_ETH_USE_SPI_ETHERNET 1 +#define CONFIG_ESP_EVENT_POST_FROM_ISR 1 +#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1 +#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1 +#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512 +#define CONFIG_HTTPD_MAX_URI_LEN 512 +#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1 +#define CONFIG_HTTPD_PURGE_BUF_LEN 32 +#endif +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1 +#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR 1 +#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4 +#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1 +#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1 +#define CONFIG_RTC_CLK_SRC_INT_RC 1 +#define CONFIG_RTC_CLK_CAL_CYCLES 1024 +#define CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB 1 +#define CONFIG_MMU_PAGE_SIZE_64KB 1 +#define CONFIG_MMU_PAGE_MODE "64KB" +#define CONFIG_MMU_PAGE_SIZE 0x10000 +#define CONFIG_ESP32C3_REV_MIN_3 1 +#define CONFIG_ESP32C3_REV_MIN 3 +#define CONFIG_XTAL_FREQ_40 1 +#define CONFIG_XTAL_FREQ 40 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE 32 +#define CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL 120 +#define CONFIG_ESP_NETIF_TCPIP_LWIP 1 +#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20 +#define CONFIG_ESP_PHY_MAX_TX_POWER 20 +#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1 +#define CONFIG_ESP_PHY_ENABLE_USB 1 +#endif +/* ESP-IDF v6.1's sleep_modes.c reaches for the PAU-only + sleep_enable_cpu_retention() when the CPU is powered down in light sleep, + which the ESP32-C3 has no support for (SOC_PAU_SUPPORTED is 0 there). + The RT-Thread port does its own tick/sleep handling, so leave the + ESP-IDF power management off. */ +#ifdef CONFIG_PM_ENABLE +#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1 +#endif +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1 +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160 +/* new in ESP-IDF v6.1 (components/esp_hw_support/Kconfig), default 0 */ +#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0 +#ifdef BSP_ENABLE_GDBSTUB +#define CONFIG_ESP_SYSTEM_PANIC_GDBSTUB 1 +#else +#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 +#endif +#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 +#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1 +#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_SYSTEM_USE_EH_FRAME 1 +#endif +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_PMS 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 1 +#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304 +#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1 +#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0 +#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048 +#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1 +#define CONFIG_ESP_CONSOLE_UART 1 +#define CONFIG_ESP_CONSOLE_UART_NUM 0 +#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200 +#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1 +#define CONFIG_ESP_BROWNOUT_DET 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL 7 +#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024 +#endif +#define CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER 1 +#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1 +#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1 +#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP32_WIFI_ENABLED 1 +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1 +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_ESP32_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_ESP32_WIFI_RX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_NVS_ENABLED 1 +#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752 +#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32 +#define CONFIG_ESP32_WIFI_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1 +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA 1 +#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1 +#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1 +#define CONFIG_FATFS_VOLUME_COUNT 2 +#define CONFIG_FATFS_SECTOR_4096 1 +#define CONFIG_FATFS_SECTORS_PER_CLUSTER_1 1 +#define CONFIG_FATFS_CODEPAGE_437 1 +#define CONFIG_FATFS_AUTO_TYPE 1 +#define CONFIG_FATFS_CODEPAGE 437 +#define CONFIG_FATFS_LFN_NONE 1 +#define CONFIG_FATFS_FS_LOCK 0 +#define CONFIG_FATFS_TIMEOUT_MS 10000 +#define CONFIG_FATFS_PER_FILE_CACHE 1 +#endif +#define CONFIG_FREERTOS_UNICORE 1 +#define CONFIG_FREERTOS_HZ 100 +#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE 1 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536 +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1 +#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048 +#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10 +#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 +#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1 +#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1 +#define CONFIG_FREERTOS_ISR_STACKSIZE 1536 +#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1 +#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1 +#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1 +#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1 +#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1 +#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF +#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1 +#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1 +#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2 +#define CONFIG_HEAP_POISONING_DISABLED 1 +#define CONFIG_HEAP_TRACING_OFF 1 +#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1 +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1 +#define CONFIG_LOG_MAXIMUM_LEVEL 3 +#define CONFIG_LOG_COLORS 1 +#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif" +#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1 +#define CONFIG_LWIP_TIMERS_ONDEMAND 1 +#define CONFIG_LWIP_MAX_SOCKETS 10 +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_LWIP_SO_REUSE_RXTOALL 1 +#define CONFIG_LWIP_IP4_FRAG 1 +#define CONFIG_LWIP_IP6_FRAG 1 +#define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1 +#define CONFIG_LWIP_GARP_TMR_INTERVAL 60 +#define CONFIG_LWIP_TCPIP_RECVMBOX_SIZE 32 +#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1 +#define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1 +#define CONFIG_LWIP_DHCP_OPTIONS_LEN 68 +#define CONFIG_LWIP_NUM_NETIF_CLIENT_DATA 0 +#define CONFIG_LWIP_DHCPS 1 +#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60 +#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8 +#define CONFIG_LWIP_IPV6 1 +#define CONFIG_LWIP_IPV6_NUM_ADDRESSES 3 +#define CONFIG_LWIP_NETIF_LOOPBACK 1 +#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8 +#define CONFIG_LWIP_MAX_ACTIVE_TCP 16 +#define CONFIG_LWIP_MAX_LISTENING_TCP 16 +#define CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION 1 +#define CONFIG_LWIP_TCP_MAXRTX 12 +#define CONFIG_LWIP_TCP_SYNMAXRTX 12 +#define CONFIG_LWIP_TCP_MSS 1440 +#define CONFIG_LWIP_TCP_TMR_INTERVAL 250 +#define CONFIG_LWIP_TCP_MSL 60000 +#define CONFIG_LWIP_TCP_SND_BUF_DEFAULT 5744 +#define CONFIG_LWIP_TCP_WND_DEFAULT 5744 +#define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1 +#define CONFIG_LWIP_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_TCP_RTO_TIME 1500 +#define CONFIG_LWIP_MAX_UDP_PCBS 16 +#define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_CHECKSUM_CHECK_ICMP 1 +#define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 3072 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY 1 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x7FFFFFFF +#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3 +#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5 +#define CONFIG_LWIP_ICMP 1 +#define CONFIG_LWIP_MAX_RAW_PCBS 16 +#define CONFIG_LWIP_SNTP_MAX_SERVERS 1 +#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000 +#define CONFIG_LWIP_BRIDGEIF_MAX_PORTS 7 +#define CONFIG_LWIP_ESP_LWIP_ASSERT 1 +#define CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT 1 +#define CONFIG_LWIP_HOOK_IP6_ROUTE_NONE 1 +#define CONFIG_LWIP_HOOK_ND6_GET_GW_NONE 1 +#define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1 +#define CONFIG_LWIP_HOOK_IP6_INPUT_NONE 1 +#endif +#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1 +#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1 +#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384 +#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096 +#define CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT 1 +#define CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS 200 +#define CONFIG_MBEDTLS_ECP_RESTARTABLE 1 +#define CONFIG_MBEDTLS_CMAC_C 1 +#define CONFIG_MBEDTLS_HARDWARE_AES 1 +#define CONFIG_MBEDTLS_AES_USE_INTERRUPT 1 +#define CONFIG_MBEDTLS_HARDWARE_MPI 1 +#define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1 +#define CONFIG_MBEDTLS_HARDWARE_SHA 1 +#define CONFIG_MBEDTLS_ROM_MD5 1 +#define CONFIG_MBEDTLS_HAVE_TIME 1 +#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1 +#define CONFIG_MBEDTLS_SHA512_C 1 +#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_SERVER 1 +#define CONFIG_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_ENABLED 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1 +#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1 +#define CONFIG_MBEDTLS_SSL_ALPN 1 +#define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_AES_C 1 +#define CONFIG_MBEDTLS_CCM_C 1 +#define CONFIG_MBEDTLS_GCM_C 1 +#define CONFIG_MBEDTLS_PEM_PARSE_C 1 +#define CONFIG_MBEDTLS_PEM_WRITE_C 1 +#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1 +#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1 +#define CONFIG_MBEDTLS_ECP_C 1 +#define CONFIG_MBEDTLS_ECDH_C 1 +#define CONFIG_MBEDTLS_ECDSA_C 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1 +#define CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI 1 +#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 +#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 1 +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 1 +#endif +#define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5 +#define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072 +#define CONFIG_PTHREAD_STACK_MIN 768 +#define CONFIG_PTHREAD_TASK_CORE_DEFAULT -1 +#define CONFIG_PTHREAD_TASK_NAME_DEFAULT "pthread" +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_HAS_ROM_IMPL 1 +#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1 +#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 +#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 +#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1 +#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1 +#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_SPIFFS_CACHE 1 +#define CONFIG_SPIFFS_CACHE_WR 1 +#define CONFIG_SPIFFS_PAGE_CHECK 1 +#define CONFIG_SPIFFS_GC_MAX_RUNS 10 +#define CONFIG_SPIFFS_PAGE_SIZE 256 +#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 +#define CONFIG_SPIFFS_USE_MAGIC 1 +#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 +#define CONFIG_SPIFFS_META_LENGTH 4 +#define CONFIG_SPIFFS_USE_MTIME 1 +#define CONFIG_WS_TRANSPORT 1 +#define CONFIG_WS_BUFFER_SIZE 1024 +#define CONFIG_UNITY_ENABLE_FLOAT 1 +#define CONFIG_UNITY_ENABLE_DOUBLE 1 +#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 +#ifdef BSP_USING_BLE +#define CONFIG_VFS_SUPPORT_IO 1 +#define CONFIG_VFS_SUPPORT_DIR 1 +#define CONFIG_VFS_SUPPORT_SELECT 1 +#define CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT 1 +#define CONFIG_VFS_SUPPORT_TERMIOS 1 +#define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1 +#endif +#define CONFIG_WL_SECTOR_SIZE_4096 1 +#define CONFIG_WL_SECTOR_SIZE 4096 +#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16 +#define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30 +#define CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION 1 +#define CONFIG_WPA_MBEDTLS_CRYPTO 1 +#define CONFIG_WPA_MBEDTLS_TLS_CLIENT 1 +#endif +/* List of deprecated options */ +#define CONFIG_ESP_SYSTEM_MEMPROT CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_BT_NIMBLE_MSYS1_BLOCK_COUNT CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT +#define CONFIG_BT_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE +#endif +#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART +#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE +#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT +#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_ESP32C3_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_ESP32C3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#define CONFIG_ESP32C3_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 +#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND +#define CONFIG_ESP32C3_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK +#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES +#define CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC +#define CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE +#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE CONFIG_APPTRACE_LOCK_ENABLE +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE +#define CONFIG_ESP32_PHY_MAX_TX_POWER CONFIG_ESP_PHY_MAX_TX_POWER +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER +#endif +#define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN +#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT CONFIG_PTHREAD_TASK_CORE_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT CONFIG_PTHREAD_TASK_PRIO_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT +#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER +#define CONFIG_ESP_GRATUITOUS_ARP CONFIG_LWIP_ESP_GRATUITOUS_ARP +#define CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP +#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO +#define CONFIG_GARP_TMR_INTERVAL CONFIG_LWIP_GARP_TMR_INTERVAL +#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT +#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS +#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE +#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL +#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO +#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE +#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD +#ifdef BSP_USING_BLE +#define CONFIG_NIMBLE_ACL_BUF_COUNT CONFIG_BT_NIMBLE_ACL_BUF_COUNT +#define CONFIG_NIMBLE_ACL_BUF_SIZE CONFIG_BT_NIMBLE_ACL_BUF_SIZE +#define CONFIG_NIMBLE_ATT_PREFERRED_MTU CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU +#define CONFIG_NIMBLE_CRYPTO_STACK_MBEDTLS CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS +#define CONFIG_NIMBLE_ENABLED CONFIG_BT_NIMBLE_ENABLED +#define CONFIG_NIMBLE_GAP_DEVICE_NAME_MAX_LEN CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN +#define CONFIG_NIMBLE_HCI_EVT_BUF_SIZE CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE +#define CONFIG_NIMBLE_HCI_EVT_HI_BUF_COUNT CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT +#define CONFIG_NIMBLE_HCI_EVT_LO_BUF_COUNT CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT +#define CONFIG_NIMBLE_L2CAP_COC_MAX_NUM CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM +#define CONFIG_NIMBLE_MAX_BONDS CONFIG_BT_NIMBLE_MAX_BONDS +#define CONFIG_NIMBLE_MAX_CCCDS CONFIG_BT_NIMBLE_MAX_CCCDS +#define CONFIG_NIMBLE_MAX_CONNECTIONS CONFIG_BT_NIMBLE_MAX_CONNECTIONS +#define CONFIG_NIMBLE_MEM_ALLOC_MODE_INTERNAL CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL +#define CONFIG_NIMBLE_PINNED_TO_CORE CONFIG_BT_NIMBLE_PINNED_TO_CORE +#define CONFIG_NIMBLE_ROLE_BROADCASTER CONFIG_BT_NIMBLE_ROLE_BROADCASTER +#define CONFIG_NIMBLE_ROLE_CENTRAL CONFIG_BT_NIMBLE_ROLE_CENTRAL +#define CONFIG_NIMBLE_ROLE_OBSERVER CONFIG_BT_NIMBLE_ROLE_OBSERVER +#define CONFIG_NIMBLE_ROLE_PERIPHERAL CONFIG_BT_NIMBLE_ROLE_PERIPHERAL +#define CONFIG_NIMBLE_RPA_TIMEOUT CONFIG_BT_NIMBLE_RPA_TIMEOUT +#define CONFIG_NIMBLE_SM_LEGACY CONFIG_BT_NIMBLE_SM_LEGACY +#define CONFIG_NIMBLE_SM_SC CONFIG_BT_NIMBLE_SM_SC +#define CONFIG_NIMBLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE +#define CONFIG_NIMBLE_SVC_GAP_DEVICE_NAME CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME +#define CONFIG_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE +#endif +#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE +#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL +#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR +#define CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR +#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER +#define CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS +#endif +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS +#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_SUPPORT_TERMIOS CONFIG_VFS_SUPPORT_TERMIOS +#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT +#endif +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE +#define CONFIG_TCPIP_TASK_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY +#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY +#define CONFIG_TCPIP_TASK_STACK_SIZE CONFIG_LWIP_TCPIP_TASK_STACK_SIZE +#define CONFIG_TCP_MAXRTX CONFIG_LWIP_TCP_MAXRTX +#define CONFIG_TCP_MSL CONFIG_LWIP_TCP_MSL +#define CONFIG_TCP_MSS CONFIG_LWIP_TCP_MSS +#define CONFIG_TCP_OVERSIZE_MSS CONFIG_LWIP_TCP_OVERSIZE_MSS +#define CONFIG_TCP_QUEUE_OOSEQ CONFIG_LWIP_TCP_QUEUE_OOSEQ +#define CONFIG_TCP_RECVMBOX_SIZE CONFIG_LWIP_TCP_RECVMBOX_SIZE +#define CONFIG_TCP_SND_BUF_DEFAULT CONFIG_LWIP_TCP_SND_BUF_DEFAULT +#define CONFIG_TCP_SYNMAXRTX CONFIG_LWIP_TCP_SYNMAXRTX +#define CONFIG_TCP_WND_DEFAULT CONFIG_LWIP_TCP_WND_DEFAULT +#endif +#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE +#endif +#endif diff --git a/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig_c6.h b/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig_c6.h new file mode 100644 index 000000000000..4831c4b22c3e --- /dev/null +++ b/bsp/ESP/ESP32_C6/libraries/drivers/sdkconfig_c6.h @@ -0,0 +1,940 @@ +/* ESP32-C6 configuration. + * Non-SOC options follow the shared C3 header, with the target set to + * esp32c6 and flash size set to 8MB (this DevKitC-1 module). + * SOC options are the ESP-IDF v5.1.4 soc_caps.h macros. + */ +#pragma once + +#define CONFIG_IDF_CMAKE 1 +#define CONFIG_IDF_TARGET_ARCH_RISCV 1 +#define CONFIG_IDF_TARGET_ARCH "riscv" +#define CONFIG_IDF_TARGET "esp32c6" +#define CONFIG_IDF_TARGET_ESP32C6 1 +#define CONFIG_IDF_RTOS_RTTHREAD 1 +#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x000D +#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1 +#define CONFIG_APP_BUILD_GENERATE_BINARIES 1 +#define CONFIG_APP_BUILD_BOOTLOADER 1 +#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0 +#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1 +#define CONFIG_BOOTLOADER_LOG_LEVEL 3 +/* C6 has no rtc_vddsdio_config_t. Leave the 1.9V boost off. */ +#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 +#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 +#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1 +#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1 +#define CONFIG_SECURE_BOOT_V2_PREFERRED 1 +#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1 +#define CONFIG_APP_COMPILE_TIME_DATE 1 +#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 +#define CONFIG_ESP_ROM_HAS_CRC_LE 1 +#define CONFIG_ESP_ROM_HAS_CRC_BE 1 +#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1 +#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1 +#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 3 +#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1 +#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1 +#define CONFIG_ESP_ROM_GET_CLK_FREQ 1 +#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1 +#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1 +#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 +#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "80m" +#define CONFIG_ESPTOOLPY_FLASHSIZE_8MB 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE "8MB" +#define CONFIG_ESPTOOLPY_BEFORE_RESET 1 +#define CONFIG_ESPTOOLPY_BEFORE "default_reset" +#define CONFIG_ESPTOOLPY_AFTER_RESET 1 +#define CONFIG_ESPTOOLPY_AFTER "hard_reset" +#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200 +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_WIFI_SSID "myssid" +#define CONFIG_ESP_WIFI_PASSWORD "mypassword" +#define CONFIG_ESP_MAXIMUM_RETRY 5 +#define CONFIG_ESP_WIFI_AUTH_WPA2_PSK 1 +#endif +#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1 +#define CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB 1 +#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2 +#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1 +#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_APPTRACE_DEST_NONE 1 +#define CONFIG_APPTRACE_DEST_UART_NONE 1 +#define CONFIG_APPTRACE_UART_TASK_PRIO 1 +#define CONFIG_APPTRACE_LOCK_ENABLE 1 +#endif +#ifdef BSP_USING_BLE +#define CONFIG_BT_ENABLED 1 +#define CONFIG_BT_NIMBLE_ENABLED 1 +#define CONFIG_BT_CONTROLLER_ENABLED 1 +#define CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL 1 +#define CONFIG_BT_NIMBLE_LOG_LEVEL_INFO 1 +#define CONFIG_BT_NIMBLE_LOG_LEVEL 1 +#define CONFIG_BT_NIMBLE_MAX_CONNECTIONS 3 +#define CONFIG_BT_NIMBLE_MAX_BONDS 3 +#define CONFIG_BT_NIMBLE_MAX_CCCDS 8 +#define CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM 0 +#define CONFIG_BT_NIMBLE_PINNED_TO_CORE 0 +#define CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE 4096 +#define CONFIG_BT_NIMBLE_ROLE_CENTRAL 1 +#define CONFIG_BT_NIMBLE_ROLE_PERIPHERAL 1 +#define CONFIG_BT_NIMBLE_ROLE_BROADCASTER 1 +#define CONFIG_BT_NIMBLE_ROLE_OBSERVER 1 +#define CONFIG_BT_NIMBLE_SECURITY_ENABLE 1 +#define CONFIG_BT_NIMBLE_SM_LEGACY 1 +#define CONFIG_BT_NIMBLE_SM_SC 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_ENCRYPTION 1 +#define CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME "nimble" +#define CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN 31 +#define CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU 256 +#define CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE 0x0 +#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT 12 +#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_SIZE 256 +#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_COUNT 24 +#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_SIZE 320 +#define CONFIG_BT_NIMBLE_ACL_BUF_COUNT 24 +#define CONFIG_BT_NIMBLE_ACL_BUF_SIZE 255 +#define CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE 70 +#define CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT 30 +#define CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT 8 +#define CONFIG_BT_NIMBLE_GATT_MAX_PROCS 4 +#define CONFIG_BT_NIMBLE_RPA_TIMEOUT 900 +#define CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS 1 +#define CONFIG_BT_NIMBLE_HS_STOP_TIMEOUT_MS 2000 +#define CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT 1 +#define CONFIG_BT_NIMBLE_MAX_CONN_REATTEMPT 3 +#define CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY 1 +#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_CODED_PHY 1 +#define CONFIG_BT_NIMBLE_MAX_PERIODIC_SYNCS 0 +#define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1 +#define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_EFF 0 +#define CONFIG_BT_NIMBLE_WHITELIST_SIZE 12 +#define CONFIG_BT_NIMBLE_USE_ESP_TIMER 1 +#define CONFIG_BT_NIMBLE_LEGACY_VHCI_ENABLE 1 +#define CONFIG_BT_CTRL_MODE_EFF 1 +#define CONFIG_BT_CTRL_BLE_MAX_ACT 10 +#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10 +#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0 +#define CONFIG_BT_CTRL_PINNED_TO_CORE 0 +#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1 +#define CONFIG_BT_CTRL_HCI_TL 1 +#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30 +#define CONFIG_BT_CTRL_HW_CCA_VAL 20 +#define CONFIG_BT_CTRL_HW_CCA_EFF 0 +#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1 +#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0 +#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1 +#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0 +#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1 +#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0 +#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P3 1 +#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 9 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100 +#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20 +#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1 +#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1 +#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0 +#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100 +#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1 +#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0 +#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0 +#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0 +#define CONFIG_BT_CTRL_HCI_TL_EFF 1 +#endif +#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1 +#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1 +#define CONFIG_EFUSE_MAX_BLK_LEN 256 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_TLS_USING_MBEDTLS 1 +#define CONFIG_ESP_TLS_USE_DS_PERIPHERAL 1 +#endif +#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ETH_ENABLED 1 +#define CONFIG_ETH_USE_SPI_ETHERNET 1 +#define CONFIG_ESP_EVENT_POST_FROM_ISR 1 +#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1 +#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1 +#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512 +#define CONFIG_HTTPD_MAX_URI_LEN 512 +#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1 +#define CONFIG_HTTPD_PURGE_BUF_LEN 32 +#endif +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1 +#define CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR 1 +#define CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES 4 +#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1 +#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1 +#define CONFIG_RTC_CLK_SRC_INT_RC 1 +#define CONFIG_RTC_CLK_CAL_CYCLES 1024 +#define CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB 1 +#define CONFIG_MMU_PAGE_SIZE_64KB 1 +#define CONFIG_MMU_PAGE_MODE "64KB" +#define CONFIG_MMU_PAGE_SIZE 0x10000 +#define CONFIG_ESP32C6_REV_MIN_0 1 +#define CONFIG_ESP32C6_REV_MIN 0 +#define CONFIG_XTAL_FREQ_40 1 +#define CONFIG_XTAL_FREQ 40 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE 32 +#define CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL 120 +#define CONFIG_ESP_NETIF_TCPIP_LWIP 1 +#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20 +#define CONFIG_ESP_PHY_MAX_TX_POWER 20 +#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1 +#define CONFIG_ESP_PHY_ENABLE_USB 1 +#endif +#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1 +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1 +#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160 +#ifdef BSP_ENABLE_GDBSTUB +#define CONFIG_ESP_SYSTEM_PANIC_GDBSTUB 1 +#else +#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 +#endif +#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 +#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1 +#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_SYSTEM_USE_EH_FRAME 1 +#endif +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 0 +#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 0 +#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304 +#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1 +#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0 +#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048 +#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1 +#define CONFIG_ESP_CONSOLE_UART 1 +#define CONFIG_ESP_CONSOLE_UART_NUM 0 +#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200 +#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1 +#define CONFIG_ESP_BROWNOUT_DET 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1 +#define CONFIG_ESP_BROWNOUT_DET_LVL 7 +#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR 0 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024 +#endif +#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1 +#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1 +#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP32_WIFI_ENABLED 1 +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1 +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_ESP32_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_ESP32_WIFI_RX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_NVS_ENABLED 1 +#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752 +#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32 +#define CONFIG_ESP32_WIFI_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1 +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1 +#define CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA 1 +#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1 +#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1 +#define CONFIG_FATFS_VOLUME_COUNT 2 +#define CONFIG_FATFS_SECTOR_4096 1 +#define CONFIG_FATFS_SECTORS_PER_CLUSTER_1 1 +#define CONFIG_FATFS_CODEPAGE_437 1 +#define CONFIG_FATFS_AUTO_TYPE 1 +#define CONFIG_FATFS_CODEPAGE 437 +#define CONFIG_FATFS_LFN_NONE 1 +#define CONFIG_FATFS_FS_LOCK 0 +#define CONFIG_FATFS_TIMEOUT_MS 10000 +#define CONFIG_FATFS_PER_FILE_CACHE 1 +#endif +#define CONFIG_FREERTOS_UNICORE 1 +#define CONFIG_FREERTOS_HZ 100 +#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE 1 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536 +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1 +#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048 +#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10 +#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 +#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1 +#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1 +#define CONFIG_FREERTOS_ISR_STACKSIZE 1536 +#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1 +#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1 +#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1 +#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1 +#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1 +#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF +#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1 +#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1 +#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2 +#define CONFIG_HEAP_POISONING_DISABLED 1 +#define CONFIG_HEAP_TRACING_OFF 1 +#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1 +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1 +#define CONFIG_LOG_MAXIMUM_LEVEL 3 +#define CONFIG_LOG_COLORS 1 +#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif" +#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1 +#define CONFIG_LWIP_TIMERS_ONDEMAND 1 +#define CONFIG_LWIP_MAX_SOCKETS 10 +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_LWIP_SO_REUSE_RXTOALL 1 +#define CONFIG_LWIP_IP4_FRAG 1 +#define CONFIG_LWIP_IP6_FRAG 1 +#define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1 +#define CONFIG_LWIP_GARP_TMR_INTERVAL 60 +#define CONFIG_LWIP_TCPIP_RECVMBOX_SIZE 32 +#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1 +#define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1 +#define CONFIG_LWIP_DHCP_OPTIONS_LEN 68 +#define CONFIG_LWIP_NUM_NETIF_CLIENT_DATA 0 +#define CONFIG_LWIP_DHCPS 1 +#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60 +#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8 +#define CONFIG_LWIP_IPV6 1 +#define CONFIG_LWIP_IPV6_NUM_ADDRESSES 3 +#define CONFIG_LWIP_NETIF_LOOPBACK 1 +#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8 +#define CONFIG_LWIP_MAX_ACTIVE_TCP 16 +#define CONFIG_LWIP_MAX_LISTENING_TCP 16 +#define CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION 1 +#define CONFIG_LWIP_TCP_MAXRTX 12 +#define CONFIG_LWIP_TCP_SYNMAXRTX 12 +#define CONFIG_LWIP_TCP_MSS 1440 +#define CONFIG_LWIP_TCP_TMR_INTERVAL 250 +#define CONFIG_LWIP_TCP_MSL 60000 +#define CONFIG_LWIP_TCP_SND_BUF_DEFAULT 5744 +#define CONFIG_LWIP_TCP_WND_DEFAULT 5744 +#define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1 +#define CONFIG_LWIP_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_TCP_RTO_TIME 1500 +#define CONFIG_LWIP_MAX_UDP_PCBS 16 +#define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6 +#define CONFIG_LWIP_CHECKSUM_CHECK_ICMP 1 +#define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 3072 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY 1 +#define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x7FFFFFFF +#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3 +#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5 +#define CONFIG_LWIP_ICMP 1 +#define CONFIG_LWIP_MAX_RAW_PCBS 16 +#define CONFIG_LWIP_SNTP_MAX_SERVERS 1 +#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000 +#define CONFIG_LWIP_BRIDGEIF_MAX_PORTS 7 +#define CONFIG_LWIP_ESP_LWIP_ASSERT 1 +#define CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT 1 +#define CONFIG_LWIP_HOOK_IP6_ROUTE_NONE 1 +#define CONFIG_LWIP_HOOK_ND6_GET_GW_NONE 1 +#define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1 +#define CONFIG_LWIP_HOOK_IP6_INPUT_NONE 1 +#endif +#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1 +#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1 +#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384 +#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096 +#define CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT 1 +#define CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1 +#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS 200 +#define CONFIG_MBEDTLS_ECP_RESTARTABLE 1 +#define CONFIG_MBEDTLS_CMAC_C 1 +#define CONFIG_MBEDTLS_HARDWARE_MPI 1 +#define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1 +#define CONFIG_MBEDTLS_ROM_MD5 1 +#define CONFIG_MBEDTLS_HAVE_TIME 1 +#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1 +#define CONFIG_MBEDTLS_SHA512_C 1 +#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_SERVER 1 +#define CONFIG_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_ENABLED 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1 +#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1 +#define CONFIG_MBEDTLS_SSL_ALPN 1 +#define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_AES_C 1 +#define CONFIG_MBEDTLS_CCM_C 1 +#define CONFIG_MBEDTLS_GCM_C 1 +#define CONFIG_MBEDTLS_PEM_PARSE_C 1 +#define CONFIG_MBEDTLS_PEM_WRITE_C 1 +#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1 +#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1 +#define CONFIG_MBEDTLS_ECP_C 1 +#define CONFIG_MBEDTLS_ECDH_C 1 +#define CONFIG_MBEDTLS_ECDSA_C 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1 +#define CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI 1 +#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 +#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 1 +#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 1 +#endif +#define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5 +#define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072 +#define CONFIG_PTHREAD_STACK_MIN 768 +#define CONFIG_PTHREAD_TASK_CORE_DEFAULT -1 +#define CONFIG_PTHREAD_TASK_NAME_DEFAULT "pthread" +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_HAS_ROM_IMPL 1 +#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1 +#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 +#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 +#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1 +#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1 +#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1 +#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1 +#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_SPIFFS_CACHE 1 +#define CONFIG_SPIFFS_CACHE_WR 1 +#define CONFIG_SPIFFS_PAGE_CHECK 1 +#define CONFIG_SPIFFS_GC_MAX_RUNS 10 +#define CONFIG_SPIFFS_PAGE_SIZE 256 +#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 +#define CONFIG_SPIFFS_USE_MAGIC 1 +#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 +#define CONFIG_SPIFFS_META_LENGTH 4 +#define CONFIG_SPIFFS_USE_MTIME 1 +#define CONFIG_WS_TRANSPORT 1 +#define CONFIG_WS_BUFFER_SIZE 1024 +#define CONFIG_UNITY_ENABLE_FLOAT 1 +#define CONFIG_UNITY_ENABLE_DOUBLE 1 +#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 +#ifdef BSP_USING_BLE +#define CONFIG_VFS_SUPPORT_IO 1 +#define CONFIG_VFS_SUPPORT_DIR 1 +#define CONFIG_VFS_SUPPORT_SELECT 1 +#define CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT 1 +#define CONFIG_VFS_SUPPORT_TERMIOS 1 +#define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1 +#endif +#define CONFIG_WL_SECTOR_SIZE_4096 1 +#define CONFIG_WL_SECTOR_SIZE 4096 +#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16 +#define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30 +#define CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION 1 +#define CONFIG_WPA_MBEDTLS_CRYPTO 1 +#define CONFIG_WPA_MBEDTLS_TLS_CLIENT 1 +#endif +/* List of deprecated options */ +#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_BT_NIMBLE_MSYS1_BLOCK_COUNT CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT +#define CONFIG_BT_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE +#endif +#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART +#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE +#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT +#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_ESP32C6_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET +#define CONFIG_ESP32C6_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL +#define CONFIG_ESP32C6_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 +#define CONFIG_ESP32C6_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE +#define CONFIG_ESP32C6_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 +#define CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ +#define CONFIG_ESP32C6_LIGHTSLEEP_GPIO_RESET_WORKAROUND CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND +#define CONFIG_ESP32C6_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define CONFIG_ESP32C6_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK +#define CONFIG_ESP32C6_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES +#define CONFIG_ESP32C6_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC +#define CONFIG_ESP32C6_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE +#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE CONFIG_APPTRACE_LOCK_ENABLE +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE +#define CONFIG_ESP32_PHY_MAX_TX_POWER CONFIG_ESP_PHY_MAX_TX_POWER +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER +#endif +#define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN +#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT CONFIG_PTHREAD_TASK_CORE_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT CONFIG_PTHREAD_TASK_PRIO_DEFAULT +#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT +#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER +#define CONFIG_ESP_GRATUITOUS_ARP CONFIG_LWIP_ESP_GRATUITOUS_ARP +#define CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP +#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO +#define CONFIG_GARP_TMR_INTERVAL CONFIG_LWIP_GARP_TMR_INTERVAL +#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT +#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS +#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE +#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL +#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO +#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE +#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD +#ifdef BSP_USING_BLE +#define CONFIG_NIMBLE_ACL_BUF_COUNT CONFIG_BT_NIMBLE_ACL_BUF_COUNT +#define CONFIG_NIMBLE_ACL_BUF_SIZE CONFIG_BT_NIMBLE_ACL_BUF_SIZE +#define CONFIG_NIMBLE_ATT_PREFERRED_MTU CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU +#define CONFIG_NIMBLE_CRYPTO_STACK_MBEDTLS CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS +#define CONFIG_NIMBLE_ENABLED CONFIG_BT_NIMBLE_ENABLED +#define CONFIG_NIMBLE_GAP_DEVICE_NAME_MAX_LEN CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN +#define CONFIG_NIMBLE_HCI_EVT_BUF_SIZE CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE +#define CONFIG_NIMBLE_HCI_EVT_HI_BUF_COUNT CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT +#define CONFIG_NIMBLE_HCI_EVT_LO_BUF_COUNT CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT +#define CONFIG_NIMBLE_L2CAP_COC_MAX_NUM CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM +#define CONFIG_NIMBLE_MAX_BONDS CONFIG_BT_NIMBLE_MAX_BONDS +#define CONFIG_NIMBLE_MAX_CCCDS CONFIG_BT_NIMBLE_MAX_CCCDS +#define CONFIG_NIMBLE_MAX_CONNECTIONS CONFIG_BT_NIMBLE_MAX_CONNECTIONS +#define CONFIG_NIMBLE_MEM_ALLOC_MODE_INTERNAL CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL +#define CONFIG_NIMBLE_PINNED_TO_CORE CONFIG_BT_NIMBLE_PINNED_TO_CORE +#define CONFIG_NIMBLE_ROLE_BROADCASTER CONFIG_BT_NIMBLE_ROLE_BROADCASTER +#define CONFIG_NIMBLE_ROLE_CENTRAL CONFIG_BT_NIMBLE_ROLE_CENTRAL +#define CONFIG_NIMBLE_ROLE_OBSERVER CONFIG_BT_NIMBLE_ROLE_OBSERVER +#define CONFIG_NIMBLE_ROLE_PERIPHERAL CONFIG_BT_NIMBLE_ROLE_PERIPHERAL +#define CONFIG_NIMBLE_RPA_TIMEOUT CONFIG_BT_NIMBLE_RPA_TIMEOUT +#define CONFIG_NIMBLE_SM_LEGACY CONFIG_BT_NIMBLE_SM_LEGACY +#define CONFIG_NIMBLE_SM_SC CONFIG_BT_NIMBLE_SM_SC +#define CONFIG_NIMBLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE +#define CONFIG_NIMBLE_SVC_GAP_DEVICE_NAME CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME +#define CONFIG_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE +#endif +#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE +#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL +#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR +#define CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR +#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER +#define CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS +#endif +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS +#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_SUPPORT_TERMIOS CONFIG_VFS_SUPPORT_TERMIOS +#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT +#endif +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE +#define CONFIG_TCPIP_TASK_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY +#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY +#define CONFIG_TCPIP_TASK_STACK_SIZE CONFIG_LWIP_TCPIP_TASK_STACK_SIZE +#define CONFIG_TCP_MAXRTX CONFIG_LWIP_TCP_MAXRTX +#define CONFIG_TCP_MSL CONFIG_LWIP_TCP_MSL +#define CONFIG_TCP_MSS CONFIG_LWIP_TCP_MSS +#define CONFIG_TCP_OVERSIZE_MSS CONFIG_LWIP_TCP_OVERSIZE_MSS +#define CONFIG_TCP_QUEUE_OOSEQ CONFIG_LWIP_TCP_QUEUE_OOSEQ +#define CONFIG_TCP_RECVMBOX_SIZE CONFIG_LWIP_TCP_RECVMBOX_SIZE +#define CONFIG_TCP_SND_BUF_DEFAULT CONFIG_LWIP_TCP_SND_BUF_DEFAULT +#define CONFIG_TCP_SYNMAXRTX CONFIG_LWIP_TCP_SYNMAXRTX +#define CONFIG_TCP_WND_DEFAULT CONFIG_LWIP_TCP_WND_DEFAULT +#endif +#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH +#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY +#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH +#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE +#if defined(BSP_USING_WIFI) || defined(BSP_USING_BLE) +#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE +#endif + +#define CONFIG_SOC_ADC_SUPPORTED 1 +#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1 +#define CONFIG_SOC_UART_SUPPORTED 1 +#define CONFIG_SOC_GDMA_SUPPORTED 1 +#define CONFIG_SOC_GPTIMER_SUPPORTED 1 +#define CONFIG_SOC_PCNT_SUPPORTED 1 +#define CONFIG_SOC_MCPWM_SUPPORTED 1 +#define CONFIG_SOC_TWAI_SUPPORTED 1 +#define CONFIG_SOC_ETM_SUPPORTED 1 +#define CONFIG_SOC_PARLIO_SUPPORTED 1 +#define CONFIG_SOC_BT_SUPPORTED 1 +#define CONFIG_SOC_IEEE802154_SUPPORTED 1 +#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1 +#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1 +#define CONFIG_SOC_WIFI_SUPPORTED 1 +#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1 +#define CONFIG_SOC_ULP_SUPPORTED 1 +#define CONFIG_SOC_LP_CORE_SUPPORTED 1 +#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1 +#define CONFIG_SOC_RTC_MEM_SUPPORTED 1 +#define CONFIG_SOC_I2S_SUPPORTED 1 +#define CONFIG_SOC_RMT_SUPPORTED 1 +#define CONFIG_SOC_SDM_SUPPORTED 1 +#define CONFIG_SOC_GPSPI_SUPPORTED 1 +#define CONFIG_SOC_LEDC_SUPPORTED 1 +#define CONFIG_SOC_I2C_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_SUPPORTED 1 +#define CONFIG_SOC_SUPPORT_COEXISTENCE 1 +#define CONFIG_SOC_AES_SUPPORTED 1 +#define CONFIG_SOC_MPI_SUPPORTED 1 +#define CONFIG_SOC_SHA_SUPPORTED 1 +#define CONFIG_SOC_HMAC_SUPPORTED 1 +#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1 +#define CONFIG_SOC_ECC_SUPPORTED 1 +#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1 +#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1 +#define CONFIG_SOC_SDIO_SLAVE_SUPPORTED 1 +#define CONFIG_SOC_BOD_SUPPORTED 1 +#define CONFIG_SOC_APM_SUPPORTED 1 +#define CONFIG_SOC_PMU_SUPPORTED 1 +#define CONFIG_SOC_PAU_SUPPORTED 1 +#define CONFIG_SOC_LP_TIMER_SUPPORTED 1 +#define CONFIG_SOC_LP_AON_SUPPORTED 1 +#define CONFIG_SOC_LP_I2C_SUPPORTED 1 +#define CONFIG_SOC_XTAL_SUPPORT_40M 1 +#define CONFIG_SOC_AES_SUPPORT_DMA (1) +#define CONFIG_SOC_AES_GDMA (1) +#define CONFIG_SOC_AES_SUPPORT_AES_128 (1) +#define CONFIG_SOC_AES_SUPPORT_AES_256 (1) +#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1 +#define CONFIG_SOC_ADC_DMA_SUPPORTED 1 +#define CONFIG_SOC_ADC_PERIPH_NUM (1U) +#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM (7) +#define CONFIG_SOC_ADC_ATTEN_NUM (4) +#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define CONFIG_SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM (2) +#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES (4) +#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH (12) +#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH (12) +#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +#define CONFIG_SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ +#define CONFIG_SOC_ADC_TEMPERATURE_SHARE_INTR (1) +#define CONFIG_SOC_APB_BACKUP_DMA (0) +#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1 +#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1 +#define CONFIG_SOC_CPU_CORES_NUM (1U) +#define CONFIG_SOC_CPU_INTR_NUM 32 +#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define CONFIG_SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller +#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 4 +#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 4 +#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes +#define CONFIG_SOC_CPU_HAS_PMA 1 +#define CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP 1 +#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) +#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) +#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) +#define CONFIG_SOC_GDMA_GROUPS (1U) // Number of GDMA groups +#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group +#define CONFIG_SOC_GDMA_SUPPORT_ETM (1) // Support ETM submodule +#define CONFIG_SOC_ETM_GROUPS 1U // Number of ETM groups +#define CONFIG_SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define CONFIG_SOC_GPIO_PORT 1U +#define CONFIG_SOC_GPIO_PIN_COUNT 31 +#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +#define CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +#define CONFIG_SOC_GPIO_SUPPORT_ETM 1 +#define CONFIG_SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +#define CONFIG_SOC_GPIO_ETM_TASKS_PER_GROUP 8 +#define CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +#define CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) +#define CONFIG_SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1) +#define CONFIG_SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK +#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) +#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL +#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD (1) +#define CONFIG_SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) +#define CONFIG_SOC_RTCIO_PIN_COUNT 8 +#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 +#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1 +#define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1 +#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ +#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ +#define CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define CONFIG_SOC_I2C_NUM (1U) +#define CONFIG_SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +#define CONFIG_SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ +#define CONFIG_SOC_I2C_SUPPORT_SLAVE (1) +#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS (1) +#define CONFIG_SOC_I2C_SUPPORT_XTAL (1) +#define CONFIG_SOC_I2C_SUPPORT_RTC (1) +#define CONFIG_SOC_LP_I2C_NUM (1U) +#define CONFIG_SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */ +#define CONFIG_SOC_I2S_NUM (1U) +#define CONFIG_SOC_I2S_HW_VERSION_2 (1) +#define CONFIG_SOC_I2S_SUPPORTS_XTAL (1) +#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M (1) +#define CONFIG_SOC_I2S_SUPPORTS_PCM (1) +#define CONFIG_SOC_I2S_SUPPORTS_PDM (1) +#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX (1) +#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES (2) +#define CONFIG_SOC_I2S_SUPPORTS_TDM (1) +#define CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +#define CONFIG_SOC_LEDC_CHANNEL_NUM (6) +#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH (20) +#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP (1) +#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) +#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) +#define CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) +#define CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) +#define CONFIG_SOC_MMU_PERIPH_NUM (1U) +#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) +#define CONFIG_SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */ +#define CONFIG_SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000U +#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8 +#define CONFIG_SOC_MPU_REGION_RO_SUPPORTED 0 +#define CONFIG_SOC_MPU_REGION_WO_SUPPORTED 0 +#define CONFIG_SOC_PCNT_GROUPS 1U +#define CONFIG_SOC_PCNT_UNITS_PER_GROUP 4 +#define CONFIG_SOC_PCNT_CHANNELS_PER_UNIT 2 +#define CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT 2 +#define CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 +#define CONFIG_SOC_RMT_GROUPS 1U /*!< One RMT group */ +#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */ +#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */ +#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */ +#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ +#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ +#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ +#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ +#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ +#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ +#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ +#define CONFIG_SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ +#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ +#define CONFIG_SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define CONFIG_SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +#define CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +#define CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +#define CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +#define CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has +#define CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +#define CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +#define CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +#define CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has +#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output +#define CONFIG_SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) +#define CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers +#define CONFIG_SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ +#define CONFIG_SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ +#define CONFIG_SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ +#define CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ +#define CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ +#define CONFIG_SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ +#define CONFIG_SOC_RSA_MAX_BIT_LEN (3072) +#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define CONFIG_SOC_SHA_SUPPORT_DMA (1) +#define CONFIG_SOC_SHA_SUPPORT_RESUME (1) +#define CONFIG_SOC_SHA_GDMA (1) +#define CONFIG_SOC_SHA_SUPPORT_SHA1 (1) +#define CONFIG_SOC_SHA_SUPPORT_SHA224 (1) +#define CONFIG_SOC_SHA_SUPPORT_SHA256 (1) +#define CONFIG_SOC_SDM_GROUPS 1U +#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 4 +#define CONFIG_SOC_SDM_CLK_SUPPORT_PLL_F80M 1 +#define CONFIG_SOC_SDM_CLK_SUPPORT_XTAL 1 +#define CONFIG_SOC_SPI_PERIPH_NUM 2 +#define CONFIG_SOC_SPI_MAX_CS_NUM 6 +#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1 +#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1 +#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1 +#define CONFIG_SOC_SPI_SUPPORT_CLK_PLL_F80M 1 +#define CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST 1 +#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1 +#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16 +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP (1) +#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 +#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define CONFIG_SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event +#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part +#define CONFIG_SOC_TIMER_GROUPS (2) +#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define CONFIG_SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define CONFIG_SOC_TIMER_SUPPORT_ETM (1) +#define CONFIG_SOC_MWDT_SUPPORT_XTAL (1) +#define CONFIG_SOC_TWAI_CONTROLLER_NUM 2 +#define CONFIG_SOC_TWAI_CLK_SUPPORT_XTAL 1 +#define CONFIG_SOC_TWAI_BRP_MIN 2 +#define CONFIG_SOC_TWAI_BRP_MAX 32768 +#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1 +#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +#define CONFIG_SOC_EFUSE_DIS_PAD_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1 +#define CONFIG_SOC_EFUSE_DIS_ICACHE 1 +#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block +#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1 +#define CONFIG_SOC_SECURE_BOOT_V2_ECC 1 +#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 +#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define CONFIG_SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 +#define CONFIG_SOC_UART_NUM (2) +#define CONFIG_SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define CONFIG_SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define CONFIG_SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +#define CONFIG_SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ +#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) +#define CONFIG_SOC_COEX_HW_PTI (1) +#define CONFIG_SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +#define CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ +#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE (21 * 4) +#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) +#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP (1) +#define CONFIG_SOC_PM_SUPPORT_BEACON_WAKEUP (1) +#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP (1) +#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP (1) +#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! ADC_ATTEN_DB_12). Both are enum + * constants, so the preprocessor cannot tell them apart with #ifdef; use the + * IDF version macro to keep 5.1 builds working. */ +#include "esp_idf_version.h" +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(6, 0, 0) +#define ADC_DEV_ATTEN ADC_ATTEN_DB_12 +#else +#define ADC_DEV_ATTEN ADC_ATTEN_DB_11 +#endif + #ifdef BSP_USING_ADC -#define DBG_TAG "drv.adc" -#define DBG_LVL DBG_INFO +#define DBG_TAG "drv.adc" +#define DBG_LVL DBG_INFO #include -#define EXAMPLE_READ_LEN 256 -#define GET_UNIT(x) ((x>>3) & 0x1) +#define EXAMPLE_READ_LEN 256 +#define GET_UNIT(x) ((x >> 3) & 0x1) /* esp i2c dirver class */ struct esp_adc @@ -49,8 +60,7 @@ struct esp_adc #endif }; -static struct esp_adc_config adc_config[] = -{ +static struct esp_adc_config adc_config[] = { #ifdef BSP_USING_ADC1 { .adc_id = ADC_UNIT_1, @@ -128,7 +138,7 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt #else struct esp_adc *_adc = rt_container_of(device, struct esp_adc, adc_device); - if(enabled) + if (enabled) { //-------------ADC Init---------------// adc_oneshot_unit_init_cfg_t init_config = { @@ -138,14 +148,14 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt //-------------ADC Config---------------// adc_oneshot_chan_cfg_t config = { .bitwidth = ADC_BITWIDTH_DEFAULT, - .atten = ADC_ATTEN_DB_11, + .atten = ADC_DEV_ATTEN, }; ESP_ERROR_CHECK(adc_oneshot_config_channel(_adc->handle, channel, &config)); #if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED adc_cali_curve_fitting_config_t cali_config = { .unit_id = _adc->adc_id, - .atten = ADC_ATTEN_DB_11, + .atten = ADC_DEV_ATTEN, .bitwidth = ADC_BITWIDTH_DEFAULT, }; if (adc_cali_create_scheme_curve_fitting(&cali_config, &_adc->cali_handle) == ESP_OK) @@ -241,8 +251,7 @@ static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_int8_t channel, #endif } -static const struct rt_adc_ops esp_adc_ops = -{ +static const struct rt_adc_ops esp_adc_ops = { .enabled = _adc_enabled, .convert = _adc_get_value, .get_resolution = RT_NULL, diff --git a/bsp/ESP/libraries/drivers/drv_spi.c b/bsp/ESP/libraries/drivers/drv_spi.c index cdc46bdbd55a..fcb38633e8e0 100644 --- a/bsp/ESP/libraries/drivers/drv_spi.c +++ b/bsp/ESP/libraries/drivers/drv_spi.c @@ -17,47 +17,20 @@ #include "rttypes.h" #include "sdkconfig.h" -#ifdef SOC_ESP32_C6 -/* - * Two things hal/esp32c6/include/hal/spi_ll.h needs are not reachable through - * the headers this driver includes, so they come in before hal/spi_hal.h: - * - SPI_CLK_SRC_RC_FAST / SPI_CLK_SRC_XTAL, used by its clock-selection - * helpers; they are enumerators of soc/clk_tree_defs.h, and the common - * hal/include/hal/spi_types.h does not carry them; - * - spi_command_t, the type of the command argument at spi_ll.h:1130 and - * spi_ll.h:1177, which this ESP-IDF package does not define at all. The - * values below are the base commands spi_ll.h:79-91 already lists - * (as spi_ll_base_command_t), so the two agree. - * packages/ is not touched; C3 has both names where it needs them, hence the - * SoC guard. - */ -#include "soc/clk_tree_defs.h" - -typedef enum -{ - SPI_CMD_HD_WRBUF = 0x01, /*!< Half-duplex write of the WRBUF */ - SPI_CMD_HD_RDBUF = 0x02, /*!< Half-duplex read of the RDBUF */ - SPI_CMD_HD_WRDMA = 0x03, /*!< Half-duplex write through DMA */ - SPI_CMD_HD_RDDMA = 0x04, /*!< Half-duplex read through DMA */ - SPI_CMD_HD_SEG_END = 0x05, /*!< End of a half-duplex segment */ - SPI_CMD_HD_EN_QPI = 0x06, /*!< Enter QPI mode */ - SPI_CMD_HD_WR_END = 0x07, /*!< End of a half-duplex write */ - SPI_CMD_HD_INT0 = 0x08, /*!< Internal operation 0 */ - SPI_CMD_HD_INT1 = 0x09, /*!< Internal operation 1 */ - SPI_CMD_HD_INT2 = 0x0A, /*!< Internal operation 2 */ -} spi_command_t; -#endif /* SOC_ESP32_C6 */ #include "hal/spi_hal.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/hal/include/hal/spi_types.h*/ #include "driver/gpio.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/gpio.h*/ #include "driver/spi_master.h" +/* ESP-IDF v6.1's driver/spi_master.h no longer pulls in the FreeRTOS headers, + * but portMAX_DELAY below comes from FreeRTOS's portmacro.h. */ +#include #include "drv_spi.h" #include "drivers/dev_spi.h" #ifdef RT_USING_SPI #ifdef BSP_USING_SPI2 -#define LOG_TAG "drv.spi" +#define LOG_TAG "drv.spi" #include static struct rt_spi_bus spi_bus2; @@ -109,17 +82,16 @@ static struct esp32_spi spi_bus_obj[] = { }; /* private rt-thread spi ops function */ -static rt_err_t spi_configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_ssize_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message); +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message); -static struct rt_spi_ops esp32_spi_ops = -{ +static struct rt_spi_ops esp32_spi_ops = { .configure = spi_configure, .xfer = spixfer, }; -static rt_err_t spi_configure(struct rt_spi_device* device, - struct rt_spi_configuration* configuration) +static rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) { if (configuration == NULL) { @@ -139,14 +111,13 @@ static rt_err_t spi_configure(struct rt_spi_device* device, * rxlength are counted in. */ spi_bits_per_word = 8; - static spi_bus_config_t buscfg = - { - .miso_io_num=SPI2_IOMUX_PIN_NUM_MISO, /*MISO*/ - .mosi_io_num=SPI2_IOMUX_PIN_NUM_MOSI, /*MOSI*/ - .sclk_io_num=SPI2_IOMUX_PIN_NUM_CLK, /*CLK*/ - .quadwp_io_num=-1, /*不使用*/ - .quadhd_io_num=-1, /*不使用*/ - .max_transfer_sz=4092 /*最大传送数据长度*/ + static spi_bus_config_t buscfg = { + .miso_io_num = SPI2_IOMUX_PIN_NUM_MISO, /*MISO*/ + .mosi_io_num = SPI2_IOMUX_PIN_NUM_MOSI, /*MOSI*/ + .sclk_io_num = SPI2_IOMUX_PIN_NUM_CLK, /*CLK*/ + .quadwp_io_num = -1, /*不使用*/ + .quadhd_io_num = -1, /*不使用*/ + .max_transfer_sz = 4092 /*最大传送数据长度*/ }; esp_err_t err; @@ -168,65 +139,65 @@ static rt_err_t spi_configure(struct rt_spi_device* device, static spi_device_interface_config_t devcfg; - LOG_W("configuration->max_hz = %d \n",configuration->max_hz); - if(configuration->max_hz >= SPI_MASTER_FREQ_80M) + LOG_W("configuration->max_hz = %d \n", configuration->max_hz); + if (configuration->max_hz >= SPI_MASTER_FREQ_80M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_80M; /*/< 80MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_40M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_40M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_40M; /*/< 40MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_26M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_26M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_26M; /*/< 26.67MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_20M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_20M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_20M; /*/< 20MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_16M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_16M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_16M; /*/< 16MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_13M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_13M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_13M; /*/< 13.33MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_11M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_11M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_11M; /*/< 11.43MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_10M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_10M) { devcfg.clock_speed_hz = SPI_MASTER_FREQ_10M; /*/< 10MHz*/ } - else if(configuration->max_hz >= SPI_MASTER_FREQ_9M) + else if (configuration->max_hz >= SPI_MASTER_FREQ_9M) { - devcfg.clock_speed_hz = SPI_MASTER_FREQ_9M ; /*/< 8.89MHz*/ + devcfg.clock_speed_hz = SPI_MASTER_FREQ_9M; /*/< 8.89MHz*/ } else { - devcfg.clock_speed_hz = SPI_MASTER_FREQ_8M ; + devcfg.clock_speed_hz = SPI_MASTER_FREQ_8M; } switch (configuration->mode) { - case RT_SPI_MODE_0: /*!< CPOL = 0, CPHA = 0 */ - devcfg.mode = 0; - break; - case RT_SPI_MODE_1: /*!< CPOL = 0, CPHA = 1 */ - devcfg.mode = 1; - break; - case RT_SPI_MODE_2: /*!< CPOL = 1, CPHA = 0 */ - devcfg.mode = 2; - break; - case RT_SPI_MODE_3: /*!< CPOL = 1, CPHA = 1 */ - devcfg.mode = 3; - break; - default: - devcfg.mode = 0; - break; + case RT_SPI_MODE_0: /*!< CPOL = 0, CPHA = 0 */ + devcfg.mode = 0; + break; + case RT_SPI_MODE_1: /*!< CPOL = 0, CPHA = 1 */ + devcfg.mode = 1; + break; + case RT_SPI_MODE_2: /*!< CPOL = 1, CPHA = 0 */ + devcfg.mode = 2; + break; + case RT_SPI_MODE_3: /*!< CPOL = 1, CPHA = 1 */ + devcfg.mode = 3; + break; + default: + devcfg.mode = 0; + break; } /* todo: support changing cs_pin,queue_size or specifing spi_device_interface_config_t and @@ -241,7 +212,7 @@ static rt_err_t spi_configure(struct rt_spi_device* device, ESP_ERROR_CHECK(err); /* Although there is only one spi bus object, it will be a template for other bsps of ESP32 series */ - for(int i = 0; i < sizeof(spi_bus_obj)/sizeof(spi_bus_obj[0]); i++) + for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++) { spi_bus_obj[i].bus_name = "spi2"; spi_bus_obj[i].spi_bus = &spi_bus2; @@ -251,9 +222,8 @@ static rt_err_t spi_configure(struct rt_spi_device* device, return RT_EOK; }; -static rt_ssize_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message) +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - RT_ASSERT(device != NULL); RT_ASSERT(message != NULL); @@ -337,7 +307,8 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, RT_ASSERT(bus_name != RT_NULL); RT_ASSERT(device_name != RT_NULL); - rt_err_t result;rt_device_t busp = RT_NULL; + rt_err_t result; + rt_device_t busp = RT_NULL; struct rt_spi_device *spi_device; /* attach the device to spi bus*/ @@ -362,7 +333,7 @@ int rt_hw_spi_init(void) { int result = 0; - for(int i = 0; i < sizeof(spi_bus_obj)/sizeof(spi_bus_obj[0]); i++) + for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++) { spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i]; result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &esp32_spi_ops); @@ -378,4 +349,4 @@ int rt_hw_spi_init(void) INIT_BOARD_EXPORT(rt_hw_spi_init); #endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4*/ -#endif /* RT_USING_SPI */ \ No newline at end of file +#endif /* RT_USING_SPI */ diff --git a/bsp/ESP/libraries/drivers/drv_uart.c b/bsp/ESP/libraries/drivers/drv_uart.c index c226e2ca7a49..ae6260a263dd 100644 --- a/bsp/ESP/libraries/drivers/drv_uart.c +++ b/bsp/ESP/libraries/drivers/drv_uart.c @@ -13,6 +13,16 @@ #include #include "driver/uart.h" #include "hal/uart_hal.h" +/* hal/uart_periph.h on IDF v6.1, soc/uart_periph.h on the rtt-dev package */ +#if defined(__has_include) +#if __has_include("hal/uart_periph.h") +#include "hal/uart_periph.h" +#else +#include "soc/uart_periph.h" +#endif +#else +#include "soc/uart_periph.h" +#endif #include "sdkconfig.h" #ifdef RT_USING_SERIAL_V1 diff --git a/bsp/ESP/libraries/drivers/sdkconfig.h b/bsp/ESP/libraries/drivers/sdkconfig.h index 0f6a4eba6225..a64bcd994ac1 100644 --- a/bsp/ESP/libraries/drivers/sdkconfig.h +++ b/bsp/ESP/libraries/drivers/sdkconfig.h @@ -4,6 +4,17 @@ */ #include "rtconfig.h" #pragma once +/* + * ESP-IDF v6.1 moved the newlib compatibility shims into esp_libc. They are + * only enabled when CONFIG_LIBC_NEWLIB is set, otherwise esp_libc declares an + * empty `struct _reent` and the toolchain's fails to compile. + * The scons build links against the toolchain's newlib, so enable it. + */ +#define CONFIG_LIBC_NEWLIB 1 +/* new in ESP-IDF v6.1 (components/esp_libc/Kconfig), default 200 */ +#define CONFIG_LIBC_ASSERT_BUFFER_SIZE 200 +/* ESP-IDF v6.1 split esp_log into V1/V2 variants (components/log/Kconfig). */ +#define CONFIG_LOG_VERSION 1 #ifdef SOC_ESP32_C6 #include "sdkconfig_c6.h" #else @@ -223,7 +234,17 @@ #define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 #define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1 #define CONFIG_BOOTLOADER_LOG_LEVEL 3 +/* new in ESP-IDF v6.1 (components/bootloader/Kconfig.projbuild), default 80 */ +#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 80 +/* + * ESP-IDF v6.1 only offers the VDDSDIO boost on chips with a configurable + * VDDSDIO regulator (choice BOOTLOADER_VDDSDIO_BOOST depends on + * SOC_CONFIGURABLE_VDDSDIO_SUPPORTED). The ESP32-C3 has none and its + * soc/rtc.h no longer declares rtc_vddsdio_*_config(). + */ +#if !defined(SOC_ESP32_C3) #define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#endif #define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1 #define CONFIG_BOOTLOADER_WDT_ENABLE 1 #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 @@ -247,6 +268,11 @@ #define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 #define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1 #define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_ESPTOOLPY_FLASHMODE_VAL 3 +/* new in ESP-IDF v6.1: eFuse block revision range checked by the 2nd stage + bootloader (components/esp_hw_support/port/esp32c3/Kconfig.hw_support) */ +#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0 +#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199 #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 #define CONFIG_ESPTOOLPY_FLASHFREQ "80m" #define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1 @@ -406,9 +432,18 @@ #define CONFIG_ESP_PHY_REDUCE_TX_POWER 1 #define CONFIG_ESP_PHY_ENABLE_USB 1 #endif +/* ESP-IDF v6.1's sleep_modes.c reaches for the PAU-only + sleep_enable_cpu_retention() when the CPU is powered down in light sleep, + which the ESP32-C3 has no support for (SOC_PAU_SUPPORTED is 0 there). + The RT-Thread port does its own tick/sleep handling, so leave the + ESP-IDF power management off. */ +#ifdef CONFIG_PM_ENABLE #define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1 +#endif #define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1 #define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160 +/* new in ESP-IDF v6.1 (components/esp_hw_support/Kconfig), default 0 */ +#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0 #ifdef BSP_ENABLE_GDBSTUB #define CONFIG_ESP_SYSTEM_PANIC_GDBSTUB 1 #else @@ -421,6 +456,7 @@ #define CONFIG_ESP_SYSTEM_USE_EH_FRAME 1 #endif #define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 1 +#define CONFIG_ESP_SYSTEM_MEMPROT_PMS 1 #define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 1 #define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 #define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304 @@ -686,6 +722,7 @@ #define CONFIG_WPA_MBEDTLS_TLS_CLIENT 1 #endif /* List of deprecated options */ +#define CONFIG_ESP_SYSTEM_MEMPROT CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET #define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL #define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 diff --git a/bsp/ESP/libraries/drivers/sdkconfig_c6.h b/bsp/ESP/libraries/drivers/sdkconfig_c6.h index 1bab35d66077..4831c4b22c3e 100644 --- a/bsp/ESP/libraries/drivers/sdkconfig_c6.h +++ b/bsp/ESP/libraries/drivers/sdkconfig_c6.h @@ -921,3 +921,20 @@ #define CONFIG_SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1) #define CONFIG_SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ #define CONFIG_SOC_CAPS_NO_RESET_BY_ANA_BOD (1) + +/* -------------------------------------------------------------------------- + * ESP-IDF v6.1 additions the scons build needs. The C3 side of the hand + * written sdkconfig.h carries these; the C6 includes this header instead, so + * repeat the SoC independent ones here. + * -------------------------------------------------------------------------- */ +/* new in v6.1 (components/bootloader/Kconfig.projbuild), default 80 */ +#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 80 +/* new in v6.1: eFuse block revision range checked by the 2nd stage bootloader */ +#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0 +#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199 +/* new in v6.1 (components/esp_hw_support/Kconfig), default 0 */ +#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0 +/* new in v6.1: the PMS memory protection mode symbol */ +#define CONFIG_ESP_SYSTEM_MEMPROT_PMS 1 +#define CONFIG_ESP_SYSTEM_MEMPROT CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define CONFIG_ESPTOOLPY_FLASHMODE_VAL 3 diff --git a/tools/ci/bsp_detail.py b/tools/ci/bsp_detail.py index 7e68e16adcaf..7ae05250714e 100644 --- a/tools/ci/bsp_detail.py +++ b/tools/ci/bsp_detail.py @@ -28,7 +28,7 @@ 'riscv32-unknown-elf-gcc': 'https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz', 'llvm-arm': 'https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz', 'riscv-none-embed-gcc': 'https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz', - 'riscv32-esp-elf-gcc': 'https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz', + 'riscv32-esp-elf-gcc': 'https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz', 'clang': 'https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz', # 添加其他工具链的下载地址 } diff --git a/tools/ci/toolchain.sh b/tools/ci/toolchain.sh index c9040177efc5..32b24d981707 100755 --- a/tools/ci/toolchain.sh +++ b/tools/ci/toolchain.sh @@ -7,7 +7,7 @@ declare -A download_urls=( ["riscv64-unknown-elf-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.4/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz" ["riscv32-unknown-elf-gcc"]="https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz" ["riscv-none-embed-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz" -["riscv32-esp-elf-gcc"]="https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz" +["riscv32-esp-elf-gcc"]="https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz" ["clang"]="https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz" ["i686-atxhua-newlib-elf-gcc"]="https://github.com/atxhua/i686-atxhua-newlib-elf/releases/download/15.2.0/i686-atxhua-newlib-elf-linux.tar.gz" ["i686-atxhua-picolib-elf-gcc"]="https://github.com/atxhua/i686-atxhua-picolib-elf/releases/download/15.2.0/i686-atxhua-picolib-elf-linux.tar.gz" diff --git a/tools/ci/toolchain_bsp.yml b/tools/ci/toolchain_bsp.yml index f2698ba191c6..323c81950b5d 100644 --- a/tools/ci/toolchain_bsp.yml +++ b/tools/ci/toolchain_bsp.yml @@ -389,7 +389,7 @@ riscv32-esp-elf-gcc: - ESP32_C3 - ESP32_C6 count: 2 - download_url: https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz + download_url: https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20251204/riscv32-esp-elf-15.2.0_20251204-x86_64-linux-gnu.tar.xz riscv32-unknown-elf-gcc: bsp: - core-v-mcu/core-v-cv32e40p From fee1961d66dba4bd0b910567e8e7da5a92f262a5 Mon Sep 17 00:00:00 2001 From: Chen Moushun Date: Wed, 21 Oct 2026 17:53:49 +0800 Subject: [PATCH 2/3] ci: retrigger after esp-idf#18 merged From e40652ad02faae19ae22f6a2c32327998d9f222a Mon Sep 17 00:00:00 2001 From: Chen Moushun Date: Thu, 22 Oct 2026 10:53:11 +0800 Subject: [PATCH 3/3] bsp: ESP: fix C6 ADC for IDF 6.1 (adc_ll bus clock) Replace removed PERIPH_SARADC_MODULE with adc_ll_enable_bus_clock / adc_ll_reset_register when ESP_IDF_VERSION >= 6.0.0. --- bsp/ESP/libraries/drivers/drv_adc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/bsp/ESP/libraries/drivers/drv_adc.c b/bsp/ESP/libraries/drivers/drv_adc.c index 2c8f3aec9574..f8a422931b88 100644 --- a/bsp/ESP/libraries/drivers/drv_adc.c +++ b/bsp/ESP/libraries/drivers/drv_adc.c @@ -22,6 +22,7 @@ #include "esp_rom_sys.h" #include "esp_private/periph_ctrl.h" #include "esp_private/sar_periph_ctrl.h" +#include "hal/adc_ll.h" #else #include "esp_adc/adc_oneshot.h" #include "esp_adc/adc_cali.h" @@ -96,13 +97,22 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt { adc_on--; sar_periph_ctrl_adc_oneshot_power_release(); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(6, 0, 0) + adc_ll_enable_bus_clock(false); +#else periph_module_disable(PERIPH_SARADC_MODULE); +#endif } rt_mutex_release(&adc_lock); return RT_EOK; } +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(6, 0, 0) + adc_ll_enable_bus_clock(true); + adc_ll_reset_register(); +#else periph_module_enable(PERIPH_SARADC_MODULE); +#endif sar_periph_ctrl_adc_oneshot_power_acquire(); adc_on++;