MIPS Decode Stage

Design Scope and Assumptions

• In scope: [What this lab implements]
• Out of scope: [What this lab intentionally does not implement]
• Assumptions: [Clock frequency, reset behavior, data width, memory model, or other assumptions]
• Limitations: [Known limitations or simplified behaviors]

Requirements

Requirement	Description	Verification Method
REQ-01	[The design shall ...]	[Test case, waveform, calculation, or
inspection]
REQ-02	[The design shall ...]	[Test case, waveform, calculation, or
inspection]
REQ-03	[The design shall ...]	[Test case, waveform, calculation, or
inspection]

Architecture

Timing or Behavioral Summary

Save diagrams in the repository's images/ folder. Use relative paths so they display on GitHub.

Implementation

Source Code

File	Description
[module].v	[Primary implementation module]
[component].v	[Supporting component]
[testbench].v	[Verification testbench]

Implementation Notes

• [Explain one important design decision.]
• [Identify any parameterization, reusable module, or interface convention.]
• [Document any deliberate simplification made for this lab.]

Verification

Verification Strategy

The design is verified using [simulation, formal checks, hardware testing, or another method]. Verification covers:

• [Normal operating case]
• [Boundary or maximum-value case]
• [Reset or initialization case]
• [Invalid, stalled, or exceptional case, if applicable]

Testbench and Waveform

Save screenshots and waveform images in the repository's images/ folder. The testbench source is available here.

Results

Test Case	Expected Result	Observed Result	Status
TC-01 — [Name]	[Expected behavior]	[Observed behavior]	Pass / Fail
TC-02 — [Name]	[Expected behavior]	[Observed behavior]	Pass / Fail
TC-03 — [Name]	[Expected behavior]	[Observed behavior]	Pass / Fail

Reproduction Instructions

Tools and Versions

• Simulator / synthesis tool: [Name and version]
• Language / standard: [Verilog/SystemVerilog version]
• Operating system: [macOS, Windows, Linux, or other]
• Additional dependencies: [List any required tools or libraries]

Build and Run

# Replace these commands with the commands required for this lab.
[compile-command]
[run-command]

Expected output:

[Paste a short representative output or result here.]

Repository Organization

.
├── README.md
├── images/
│ ├── [timing-diagram-filename].png
│ └── [testbench-screenshot-filename].png
├── [source-files]
└── [testbench-files]

Known Issues and Future Improvements

• [Document any known issue, unverified behavior, or technical debt.]
• [Describe a realistic improvement or extension.]