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Fix the RGB display cache flush on ESP32-P4 and ESP32-S31 - #11632
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…4 and ESP32-S31 refresh() wrote the frame buffer back from the cache with a hand-declared Cache_WriteBack_Addr(addr, size). That is the ROM signature on ESP32-S3, but on ESP32-P4 and ESP32-S31 the ROM function takes three arguments, Cache_WriteBack_Addr(map, addr, size), so there the buffer address went in as the cache map, the length as the address, and the size was whatever was left in the register. Nothing was written back. Use esp_cache_msync() from esp_cache.h instead, as esp_lcd does. It picks the right cache operation on every chip. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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What
refresh()now flushes the frame buffer with ESP-IDF's cache call.Why
On P4 and S31 the old ROM call got the wrong arguments.
Cache_WriteBack_Addr(addr, size)esp_cache_msync.(map, addr, size)refresh()after writing all 768 KBdisplay.framebufferNo visible bug today: the bounce buffers copy the frame through the same cache.
Scope: mipidsi has the same two-argument declaration but never calls it; left alone.
AI assistance: written with Claude Code. I ran the tests above on hardware.